From: Shengyang Chen <shengyang.chen@starfivetech.com>
To: devicetree@vger.kernel.org, linux-phy@lists.infradead.org
Cc: vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
p.zabel@pengutronix.de, minda.chen@starfivetech.com,
changhuang.liang@starfivetech.com, rogerq@kernel.org,
geert+renesas@glider.be, keith.zhao@starfivetech.com,
shengyang.chen@starfivetech.com, linux-kernel@vger.kernel.org
Subject: [PATCH v5 1/2] dt-bindings: phy: Add starfive,jh7110-dphy-tx
Date: Thu, 18 Apr 2024 11:50:19 +0800 [thread overview]
Message-ID: <20240418035020.47876-2-shengyang.chen@starfivetech.com> (raw)
In-Reply-To: <20240418035020.47876-1-shengyang.chen@starfivetech.com>
StarFive SoCs like the jh7110 use a MIPI D-PHY TX
controller based on a M31 IP. Add a binding for it.
Signed-off-by: Shengyang Chen <shengyang.chen@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/phy/starfive,jh7110-dphy-tx.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
new file mode 100644
index 000000000000..4a06a2642b4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-tx.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Starfive SoC MIPI D-PHY Tx Controller
+
+maintainers:
+ - Keith Zhao <keith.zhao@starfivetech.com>
+ - Shengyang Chen <shengyang.chen@starfivetech.com>
+
+description:
+ The Starfive SoC uses the MIPI DSI D-PHY based on M31 IP to transfer
+ DSI data.
+
+properties:
+ compatible:
+ const: starfive,jh7110-dphy-tx
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: txesc
+
+ resets:
+ items:
+ - description: MIPITX_DPHY_SYS reset
+
+ reset-names:
+ items:
+ - const: sys
+
+ power-domains:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@295e0000 {
+ compatible = "starfive,jh7110-dphy-tx";
+ reg = <0x295e0000 0x10000>;
+ clocks = <&voutcrg 14>;
+ clock-names = "txesc";
+ resets = <&syscrg 10>;
+ reset-names = "sys";
+ power-domains = <&aon_syscon 0>;
+ #phy-cells = <0>;
+ };
--
2.17.1
next prev parent reply other threads:[~2024-04-18 4:05 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-18 3:50 [PATCH v5 0/2] Add JH7110 MIPI DPHY TX support Shengyang Chen
2024-04-18 3:50 ` Shengyang Chen [this message]
2024-04-18 3:50 ` [PATCH v5 2/2] phy: starfive: Add mipi dphy tx support Shengyang Chen
2024-05-13 8:13 ` [PATCH v5 0/2] Add JH7110 MIPI DPHY TX support Shengyang Chen
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