From: Bjorn Helgaas <helgaas@kernel.org>
To: LeoLiu-oc <LeoLiu-oc@zhaoxin.com>
Cc: rafael@kernel.org, lenb@kernel.org, james.morse@arm.com,
tony.luck@intel.com, bp@alien8.de, bhelgaas@google.com,
robert.moore@intel.com, linux-acpi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
acpica-devel@lists.linux.dev, CobeChen@zhaoxin.com,
TonyWWang@zhaoxin.com, ErosZhang@zhaoxin.com, LeoLiu@zhaoxin.com
Subject: Re: [PATCH v2 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge
Date: Wed, 8 May 2024 17:10:09 -0500 [thread overview]
Message-ID: <20240508221009.GA1791183@bhelgaas> (raw)
In-Reply-To: <20231218030430.783495-3-LeoLiu-oc@zhaoxin.com>
On Mon, Dec 18, 2023 at 11:04:29AM +0800, LeoLiu-oc wrote:
> From: LeoLiuoc <LeoLiu-oc@zhaoxin.com>
>
> Define secondary uncorrectable error mask register, secondary
> uncorrectable error severity register and secondary error capabilities and
> control register bits in AER capability for PCIe to PCI/PCI-X Bridge.
> Please refer to PCIe to PCI/PCI-X Bridge Specification, sec 5.2.3.2,
> 5.2.3.3 and 5.2.3.4.
Please include the spec revision. The only one I'm aware of is r1.0.
> Signed-off-by: LeoLiuoc <LeoLiu-oc@zhaoxin.com>
> ---
> include/uapi/linux/pci_regs.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index a39193213ff2..987c513192e8 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -802,6 +802,9 @@
> #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
> #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
> #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */
> +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */
> +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */
> +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */
>
> /* Virtual Channel */
> #define PCI_VC_PORT_CAP1 0x04
> --
> 2.34.1
>
next prev parent reply other threads:[~2024-05-08 22:10 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 9:16 [PATCH 0/3] Parse the HEST PCIe AER and set to relevant registers LeoLiu-oc
2023-11-15 9:16 ` [PATCH 1/3] ACPI/APEI: Add hest_parse_pcie_aer() LeoLiu-oc
2023-12-06 16:35 ` Rafael J. Wysocki
2023-12-14 2:57 ` LeoLiu-oc
2023-11-15 9:16 ` [PATCH 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge LeoLiu-oc
2023-11-15 9:16 ` [PATCH 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() LeoLiu-oc
2023-12-06 23:08 ` Bjorn Helgaas
2023-12-14 2:54 ` LeoLiu-oc
2023-12-18 3:04 ` [PATCH v2 0/3] Parse the HEST PCIe AER and set to relevant registers LeoLiu-oc
2023-12-18 3:04 ` [PATCH v2 1/3] ACPI/APEI: Add hest_parse_pcie_aer() LeoLiu-oc
2023-12-18 3:04 ` [PATCH v2 2/3] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge LeoLiu-oc
2024-05-08 22:10 ` Bjorn Helgaas [this message]
2024-05-09 8:42 ` LeoLiu-oc
2023-12-18 3:04 ` [PATCH v2 3/3] PCI/ACPI: Add pci_acpi_program_hest_aer_params() LeoLiu-oc
2024-05-08 22:24 ` Bjorn Helgaas
2024-05-09 9:06 ` LeoLiu-oc
2024-05-08 22:04 ` [PATCH v2 0/3] Parse the HEST PCIe AER and set to relevant registers Bjorn Helgaas
2024-05-09 8:39 ` LeoLiu-oc
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