From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: "Sunil V L" <sunilvl@ventanamicro.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
linux-serial@vger.kernel.org, acpica-devel@lists.linux.dev,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Will Deacon" <will@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"Len Brown" <lenb@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Jiri Slaby" <jirislaby@kernel.org>,
"Robert Moore" <robert.moore@intel.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Marc Zyngier" <maz@kernel.org>,
"Atish Kumar Patra" <atishp@rivosinc.com>,
"Andrei Warkentin" <andrei.warkentin@intel.com>,
"Haibo1 Xu" <haibo1.xu@intel.com>,
"Björn Töpel" <bjorn@kernel.org>
Subject: Re: [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function
Date: Thu, 2 May 2024 13:19:55 +0300 [thread overview]
Message-ID: <ZjNoy6KLtOCTe52q@smile.fi.intel.com> (raw)
In-Reply-To: <ZjNnG6JqFCZGj1qv@bogus>
On Thu, May 02, 2024 at 11:12:43AM +0100, Sudeep Holla wrote:
> On Thu, May 02, 2024 at 03:32:25PM +0530, Sunil V L wrote:
> > On Thu, May 02, 2024 at 12:24:14PM +0300, Andy Shevchenko wrote:
> > > On Wed, May 01, 2024 at 05:47:28PM +0530, Sunil V L wrote:
> > > > Add a new function for RISC-V to do any architecture specific
> > > > initialization. This function will be used to create platform devices
> > > > like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init().
> > >
> > > What is the special about this architecture that it requires a separate
> > > initialization that is _not_ going to be in other cases?
> > > Please, elaborate.
> > >
> > This init function will be used to create GSI mapping structures and in
> > future may be others like iommu. Like I mentioned, ARM already has
> > similar function acpi_arm_init(). So, it is not new right?
>
> Just to add:
>
> This is to initialise everything around all the arch specific tables
> which you will not have on any other architectures. We could execute
> on all architectures but the tables will never be found. The main point
> is why do we want to do that if we can optimise and skip on all other
> archs.
You need to carefully write the commit messages. Some kind of the above
paragraphs has to be in there.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2024-05-02 10:20 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-01 12:17 [PATCH v5 00/17] RISC-V: ACPI: Add external interrupt controller support Sunil V L
2024-05-01 12:17 ` [PATCH v5 01/17] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Sunil V L
2024-05-01 12:59 ` Will Deacon
2024-05-02 9:22 ` Andy Shevchenko
2024-05-02 9:56 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 02/17] ACPI: scan: Add a weak function to reorder the IRQCHIP probe Sunil V L
2024-05-01 12:17 ` [PATCH v5 03/17] ACPI: bus: Add acpi_riscv_init function Sunil V L
2024-05-02 9:24 ` Andy Shevchenko
2024-05-02 10:02 ` Sunil V L
2024-05-02 10:12 ` Sudeep Holla
2024-05-02 10:19 ` Andy Shevchenko [this message]
2024-05-02 11:00 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 04/17] ACPI: scan: Refactor dependency creation Sunil V L
2024-05-02 9:20 ` Andy Shevchenko
2024-05-02 9:55 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 05/17] ACPI: scan: Add RISC-V interrupt controllers to honor list Sunil V L
2024-05-01 12:17 ` [PATCH v5 06/17] ACPI: scan: Define weak function to populate dependencies Sunil V L
2024-05-01 12:17 ` [PATCH v5 07/17] ACPI: bus: Add RINTC IRQ model for RISC-V Sunil V L
2024-05-23 21:59 ` Bjorn Helgaas
2024-05-27 4:35 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 08/17] ACPI: pci_link: Clear the dependencies after probe Sunil V L
2024-05-01 16:56 ` Bjorn Helgaas
2024-05-02 9:25 ` Andy Shevchenko
2024-05-02 9:32 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 09/17] ACPI: RISC-V: Implement PCI related functionality Sunil V L
2024-05-01 12:17 ` [PATCH v5 10/17] ACPI: RISC-V: Implement function to reorder irqchip probe entries Sunil V L
2024-05-01 12:17 ` [PATCH v5 11/17] ACPI: RISC-V: Initialize GSI mapping structures Sunil V L
2024-05-01 12:17 ` [PATCH v5 12/17] ACPI: RISC-V: Implement function to add implicit dependencies Sunil V L
2024-05-01 12:17 ` [PATCH v5 13/17] irqchip/riscv-intc: Add ACPI support for AIA Sunil V L
2024-05-23 21:47 ` Thomas Gleixner
2024-05-27 4:39 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 14/17] irqchip/riscv-imsic: Add ACPI support Sunil V L
2024-05-23 22:00 ` Thomas Gleixner
2024-05-27 4:52 ` Sunil V L
2024-05-01 12:17 ` [PATCH v5 15/17] irqchip/riscv-aplic: " Sunil V L
2024-05-01 12:17 ` [PATCH v5 16/17] irqchip/sifive-plic: " Sunil V L
2024-05-01 12:17 ` [PATCH v5 17/17] serial: 8250: Add 8250_acpi driver Sunil V L
2024-05-02 9:17 ` Andy Shevchenko
2024-05-02 9:50 ` Sunil V L
2024-05-02 10:09 ` Andy Shevchenko
2024-05-02 11:20 ` Sunil V L
2024-05-02 15:35 ` Andy Shevchenko
2024-05-03 13:59 ` Sunil V L
2024-05-03 15:32 ` Andy Shevchenko
2024-05-06 11:45 ` Sunil V L
2024-05-04 15:53 ` Greg Kroah-Hartman
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