* [PATCH] ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide
@ 2013-09-17 16:46 Fabio Estevam
2013-09-20 9:01 ` Shawn Guo
0 siblings, 1 reply; 2+ messages in thread
From: Fabio Estevam @ 2013-09-17 16:46 UTC (permalink / raw
To: linux-arm-kernel
On imx6qdl-sabresd the SDHC2 and SDHC3 are 8 bit-wide, so pass the bus-width
property to reflect that.
Otherwise the mmc driver will operate with the default bus-width value of 4.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 39eafc2..64e454b 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -229,6 +229,7 @@
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
+ bus-width = <8>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
@@ -237,6 +238,7 @@
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
+ bus-width = <8>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";
--
1.8.1.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH] ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide
2013-09-17 16:46 [PATCH] ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide Fabio Estevam
@ 2013-09-20 9:01 ` Shawn Guo
0 siblings, 0 replies; 2+ messages in thread
From: Shawn Guo @ 2013-09-20 9:01 UTC (permalink / raw
To: linux-arm-kernel
On Tue, Sep 17, 2013 at 01:46:23PM -0300, Fabio Estevam wrote:
> On imx6qdl-sabresd the SDHC2 and SDHC3 are 8 bit-wide, so pass the bus-width
> property to reflect that.
>
> Otherwise the mmc driver will operate with the default bus-width value of 4.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Applied, thanks.
^ permalink raw reply [flat|nested] 2+ messages in thread
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2013-09-17 16:46 [PATCH] ARM: dts: imx6qdl-sabresd: SDHC ports are 8 bit-wide Fabio Estevam
2013-09-20 9:01 ` Shawn Guo
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