From: "Christian König" <deathsimple@vodafone.de>
To: dri-devel@lists.freedesktop.org
Subject: [PATCH 2/6] drm/radeon: properly init UVD MC bits on R600
Date: Sun, 24 Aug 2014 15:14:26 +0200 [thread overview]
Message-ID: <1408886070-31983-3-git-send-email-deathsimple@vodafone.de> (raw)
In-Reply-To: <1408886070-31983-1-git-send-email-deathsimple@vodafone.de>
From: Christian König <christian.koenig@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/radeon/r600.c | 4 ++++
drivers/gpu/drm/radeon/r600d.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c70a504..0e58d5c 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -992,6 +992,8 @@ static int r600_pcie_gart_enable(struct radeon_device *rdev)
WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
@@ -1042,6 +1044,8 @@ static void r600_pcie_gart_disable(struct radeon_device *rdev)
WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp);
+ WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp);
radeon_gart_table_vram_unpin(rdev);
}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index f94e7a9..7bfa164 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -334,7 +334,7 @@
#define MC_VM_AGP_BOT 0x2188
#define MC_VM_AGP_BASE 0x218C
#define MC_VM_FB_LOCATION 0x2180
-#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
+#define MC_VM_L1_TLB_MCB_RD_UVD_CNTL 0x2124
#define ENABLE_L1_TLB (1 << 0)
#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
#define ENABLE_L1_STRICT_ORDERING (1 << 2)
@@ -354,12 +354,14 @@
#define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15)
#define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000
#define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15
+#define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C
#define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0
#define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC
#define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204
#define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208
#define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C
#define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200
+#define MC_VM_L1_TLB_MCB_WR_UVD_CNTL 0x212c
#define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4
#define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8
#define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210
--
1.9.1
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next prev parent reply other threads:[~2014-08-24 13:15 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <UVD support for older ASICs>
2014-08-24 13:14 ` (unknown), Christian König
2014-08-24 13:14 ` [PATCH 1/6] drm/radeon: force UVD buffers into VRAM on RS[78]80 v2 Christian König
2014-08-25 17:14 ` Alex Deucher
2014-08-24 13:14 ` Christian König [this message]
2014-08-24 13:14 ` [PATCH 3/6] drm/radeon: add set_uvd_clocks callback for r6xx v4 Christian König
2014-08-24 13:14 ` [PATCH 4/6] drm/radeon: add UVD support for older asics v4 Christian König
2014-08-24 13:14 ` [PATCH 5/6] drm/radeon: implement UVD hw workarounds for R6xx v3 Christian König
2014-08-24 13:14 ` [PATCH 6/6] drm/radeon: add UVD fw names for older asic Christian König
2014-08-24 13:34 ` Mike Lothian
2014-08-25 9:10 ` Re: Christian König
2014-08-26 14:14 ` (UVD RS780 first impression) Stefan Lange
2014-08-27 3:40 ` Michel Dänzer
2014-08-27 7:00 ` Christian König
2014-08-28 19:25 ` Stefan Lange
2014-08-30 15:58 ` Stefan Lange
2014-09-07 13:24 ` Markus Trippelsdorf
2014-09-08 3:47 ` Re: Alex Deucher
2014-09-08 7:13 ` Re: Markus Trippelsdorf
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