From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423212AbbD2OB2 (ORCPT ); Wed, 29 Apr 2015 10:01:28 -0400 Received: from mga03.intel.com ([134.134.136.65]:39758 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966279AbbD2OBW (ORCPT ); Wed, 29 Apr 2015 10:01:22 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.11,671,1422950400"; d="scan'208";a="717791234" From: Shobhit Kumar To: intel-gfx , linux-kernel , linux-gpio , linux-pwm , dri-devel Cc: Linus Walleij , Alexandre Courbot , Daniel Vetter , David Airlie , Samuel Ortiz , Thierry Reding , Jani Nikula , Lee Jones , Povilas Staniulis , Chih-Wei Huang , Shobhit Kumar Subject: [PATCH 7/8] drm/i915: Use the CRC gpio for panel enable/disable Date: Wed, 29 Apr 2015 19:30:04 +0530 Message-Id: <1430316005-16480-8-git-send-email-shobhit.kumar@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1430316005-16480-1-git-send-email-shobhit.kumar@intel.com> References: <1430316005-16480-1-git-send-email-shobhit.kumar@intel.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The CRC (Crystal Cove) PMIC, controls the panel enable and disable signals for BYT for dsi panels. This is indicated in the VBT fields. Use that to initialize and use GPIO based control for these signals. v2: Use the newer gpiod interface(Alexandre) v3: Remove the redundant checks and unused code (Ville) CC: Samuel Ortiz Cc: Linus Walleij Cc: Alexandre Courbot Cc: Thierry Reding Signed-off-by: Shobhit Kumar --- drivers/gpu/drm/i915/intel_dsi.c | 32 ++++++++++++++++++++++++++++++-- drivers/gpu/drm/i915/intel_dsi.h | 6 ++++++ 2 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index 5196642..be55ffa 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "i915_drv.h" #include "intel_drv.h" #include "intel_dsi.h" @@ -415,6 +416,12 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); + /* Panel Enable over CRC PMIC */ + if (intel_dsi->gpio_panel) + gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); + + msleep(intel_dsi->panel_on_delay); + /* Disable DPOunit clock gating, can stall pipe * and we need DPLL REFA always enabled */ tmp = I915_READ(DPLL(pipe)); @@ -432,8 +439,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) /* put device in ready state */ intel_dsi_device_ready(encoder); - msleep(intel_dsi->panel_on_delay); - drm_panel_prepare(intel_dsi->panel); for_each_dsi_port(port, intel_dsi->ports) @@ -576,6 +581,10 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) msleep(intel_dsi->panel_off_delay); msleep(intel_dsi->panel_pwr_cycle_delay); + + /* Panel Disable over CRC PMIC */ + if (intel_dsi->gpio_panel) + gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); } static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, @@ -955,6 +964,11 @@ static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) /* XXX: Logically this call belongs in the panel driver. */ drm_panel_remove(intel_dsi->panel); } + + /* dispose of the gpios */ + if (intel_dsi->gpio_panel) + gpiod_put(intel_dsi->gpio_panel); + intel_encoder_destroy(encoder); } @@ -1071,6 +1085,20 @@ void intel_dsi_init(struct drm_device *dev) goto err; } + /* + * In case of BYT with CRC PMIC, we need to use GPIO for + * Panel control. + */ + if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { + intel_dsi->gpio_panel = + gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); + + if (IS_ERR(intel_dsi->gpio_panel)) { + DRM_ERROR("Failed to own gpio for panel control\n"); + intel_dsi->gpio_panel = NULL; + } + } + intel_encoder->type = INTEL_OUTPUT_DSI; intel_encoder->cloneable = 0; drm_connector_init(dev, connector, &intel_dsi_connector_funcs, diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h index 2784ac4..bf1bade 100644 --- a/drivers/gpu/drm/i915/intel_dsi.h +++ b/drivers/gpu/drm/i915/intel_dsi.h @@ -29,6 +29,9 @@ #include #include "intel_drv.h" +#define PPS_BLC_PMIC 0 +#define PPS_BLC_SOC 1 + /* Dual Link support */ #define DSI_DUAL_LINK_NONE 0 #define DSI_DUAL_LINK_FRONT_BACK 1 @@ -42,6 +45,9 @@ struct intel_dsi { struct drm_panel *panel; struct intel_dsi_host *dsi_hosts[I915_MAX_PORTS]; + /* GPIO Desc for CRC based Panel control */ + struct gpio_desc *gpio_panel; + struct intel_connector *attached_connector; /* bit mask of ports being driven */ -- 2.1.0 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shobhit Kumar Subject: [PATCH 7/8] drm/i915: Use the CRC gpio for panel enable/disable Date: Wed, 29 Apr 2015 19:30:04 +0530 Message-ID: <1430316005-16480-8-git-send-email-shobhit.kumar@intel.com> References: <1430316005-16480-1-git-send-email-shobhit.kumar@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1430316005-16480-1-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx , linux-kernel , linux-gpio , linux-pwm , dri-devel Cc: Alexandre Courbot , Samuel Ortiz , Povilas Staniulis , David Airlie , Shobhit Kumar , Linus Walleij , Jani Nikula , Chih-Wei Huang , Thierry Reding , Daniel Vetter , Lee Jones List-Id: linux-gpio@vger.kernel.org VGhlIENSQyAoQ3J5c3RhbCBDb3ZlKSBQTUlDLCBjb250cm9scyB0aGUgcGFuZWwgZW5hYmxlIGFu ZCBkaXNhYmxlCnNpZ25hbHMgZm9yIEJZVCBmb3IgZHNpIHBhbmVscy4gVGhpcyBpcyBpbmRpY2F0 ZWQgaW4gdGhlIFZCVCBmaWVsZHMuIFVzZQp0aGF0IHRvIGluaXRpYWxpemUgYW5kIHVzZSBHUElP IGJhc2VkIGNvbnRyb2wgZm9yIHRoZXNlIHNpZ25hbHMuCgp2MjogVXNlIHRoZSBuZXdlciBncGlv ZCBpbnRlcmZhY2UoQWxleGFuZHJlKQp2MzogUmVtb3ZlIHRoZSByZWR1bmRhbnQgY2hlY2tzIGFu ZCB1bnVzZWQgY29kZSAoVmlsbGUpCgpDQzogU2FtdWVsIE9ydGl6IDxzYW1lb0BsaW51eC5pbnRl bC5jb20+CkNjOiBMaW51cyBXYWxsZWlqIDxsaW51cy53YWxsZWlqQGxpbmFyby5vcmc+CkNjOiBB bGV4YW5kcmUgQ291cmJvdCA8Z251cm91QGdtYWlsLmNvbT4KQ2M6IFRoaWVycnkgUmVkaW5nIDx0 aGllcnJ5LnJlZGluZ0BnbWFpbC5jb20+ClNpZ25lZC1vZmYtYnk6IFNob2JoaXQgS3VtYXIgPHNo b2JoaXQua3VtYXJAaW50ZWwuY29tPgotLS0KIGRyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2Rz aS5jIHwgMzIgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrLS0KIGRyaXZlcnMvZ3B1L2Ry bS9pOTE1L2ludGVsX2RzaS5oIHwgIDYgKysrKysrCiAyIGZpbGVzIGNoYW5nZWQsIDM2IGluc2Vy dGlvbnMoKyksIDIgZGVsZXRpb25zKC0pCgpkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5 MTUvaW50ZWxfZHNpLmMgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kc2kuYwppbmRleCA1 MTk2NjQyLi5iZTU1ZmZhIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9k c2kuYworKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9kc2kuYwpAQCAtMzEsNiArMzEs NyBAQAogI2luY2x1ZGUgPGRybS9kcm1fcGFuZWwuaD4KICNpbmNsdWRlIDxkcm0vZHJtX21pcGlf ZHNpLmg+CiAjaW5jbHVkZSA8bGludXgvc2xhYi5oPgorI2luY2x1ZGUgPGxpbnV4L2dwaW8vY29u c3VtZXIuaD4KICNpbmNsdWRlICJpOTE1X2Rydi5oIgogI2luY2x1ZGUgImludGVsX2Rydi5oIgog I2luY2x1ZGUgImludGVsX2RzaS5oIgpAQCAtNDE1LDYgKzQxNiwxMiBAQCBzdGF0aWMgdm9pZCBp bnRlbF9kc2lfcHJlX2VuYWJsZShzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlcikKIAogCURS TV9ERUJVR19LTVMoIlxuIik7CiAKKwkvKiBQYW5lbCBFbmFibGUgb3ZlciBDUkMgUE1JQyAqLwor CWlmIChpbnRlbF9kc2ktPmdwaW9fcGFuZWwpCisJCWdwaW9kX3NldF92YWx1ZV9jYW5zbGVlcChp bnRlbF9kc2ktPmdwaW9fcGFuZWwsIDEpOworCisJbXNsZWVwKGludGVsX2RzaS0+cGFuZWxfb25f ZGVsYXkpOworCiAJLyogRGlzYWJsZSBEUE91bml0IGNsb2NrIGdhdGluZywgY2FuIHN0YWxsIHBp cGUKIAkgKiBhbmQgd2UgbmVlZCBEUExMIFJFRkEgYWx3YXlzIGVuYWJsZWQgKi8KIAl0bXAgPSBJ OTE1X1JFQUQoRFBMTChwaXBlKSk7CkBAIC00MzIsOCArNDM5LDYgQEAgc3RhdGljIHZvaWQgaW50 ZWxfZHNpX3ByZV9lbmFibGUoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIpCiAJLyogcHV0 IGRldmljZSBpbiByZWFkeSBzdGF0ZSAqLwogCWludGVsX2RzaV9kZXZpY2VfcmVhZHkoZW5jb2Rl cik7CiAKLQltc2xlZXAoaW50ZWxfZHNpLT5wYW5lbF9vbl9kZWxheSk7Ci0KIAlkcm1fcGFuZWxf cHJlcGFyZShpbnRlbF9kc2ktPnBhbmVsKTsKIAogCWZvcl9lYWNoX2RzaV9wb3J0KHBvcnQsIGlu dGVsX2RzaS0+cG9ydHMpCkBAIC01NzYsNiArNTgxLDEwIEBAIHN0YXRpYyB2b2lkIGludGVsX2Rz aV9wb3N0X2Rpc2FibGUoc3RydWN0IGludGVsX2VuY29kZXIgKmVuY29kZXIpCiAKIAltc2xlZXAo aW50ZWxfZHNpLT5wYW5lbF9vZmZfZGVsYXkpOwogCW1zbGVlcChpbnRlbF9kc2ktPnBhbmVsX3B3 cl9jeWNsZV9kZWxheSk7CisKKwkvKiBQYW5lbCBEaXNhYmxlIG92ZXIgQ1JDIFBNSUMgKi8KKwlp ZiAoaW50ZWxfZHNpLT5ncGlvX3BhbmVsKQorCQlncGlvZF9zZXRfdmFsdWVfY2Fuc2xlZXAoaW50 ZWxfZHNpLT5ncGlvX3BhbmVsLCAwKTsKIH0KIAogc3RhdGljIGJvb2wgaW50ZWxfZHNpX2dldF9o d19zdGF0ZShzdHJ1Y3QgaW50ZWxfZW5jb2RlciAqZW5jb2RlciwKQEAgLTk1NSw2ICs5NjQsMTEg QEAgc3RhdGljIHZvaWQgaW50ZWxfZHNpX2VuY29kZXJfZGVzdHJveShzdHJ1Y3QgZHJtX2VuY29k ZXIgKmVuY29kZXIpCiAJCS8qIFhYWDogTG9naWNhbGx5IHRoaXMgY2FsbCBiZWxvbmdzIGluIHRo ZSBwYW5lbCBkcml2ZXIuICovCiAJCWRybV9wYW5lbF9yZW1vdmUoaW50ZWxfZHNpLT5wYW5lbCk7 CiAJfQorCisJLyogZGlzcG9zZSBvZiB0aGUgZ3Bpb3MgKi8KKwlpZiAoaW50ZWxfZHNpLT5ncGlv X3BhbmVsKQorCQlncGlvZF9wdXQoaW50ZWxfZHNpLT5ncGlvX3BhbmVsKTsKKwogCWludGVsX2Vu Y29kZXJfZGVzdHJveShlbmNvZGVyKTsKIH0KIApAQCAtMTA3MSw2ICsxMDg1LDIwIEBAIHZvaWQg aW50ZWxfZHNpX2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRldikKIAkJZ290byBlcnI7CiAJfQog CisJLyoKKwkgKiBJbiBjYXNlIG9mIEJZVCB3aXRoIENSQyBQTUlDLCB3ZSBuZWVkIHRvIHVzZSBH UElPIGZvcgorCSAqIFBhbmVsIGNvbnRyb2wuCisJICovCisJaWYgKGRldl9wcml2LT52YnQuZHNp LmNvbmZpZy0+cHdtX2JsYyA9PSBQUFNfQkxDX1BNSUMpIHsKKwkJaW50ZWxfZHNpLT5ncGlvX3Bh bmVsID0KKwkJCWdwaW9kX2dldChkZXYtPmRldiwgInBhbmVsIiwgR1BJT0RfT1VUX0hJR0gpOwor CisJCWlmIChJU19FUlIoaW50ZWxfZHNpLT5ncGlvX3BhbmVsKSkgeworCQkJRFJNX0VSUk9SKCJG YWlsZWQgdG8gb3duIGdwaW8gZm9yIHBhbmVsIGNvbnRyb2xcbiIpOworCQkJaW50ZWxfZHNpLT5n cGlvX3BhbmVsID0gTlVMTDsKKwkJfQorCX0KKwogCWludGVsX2VuY29kZXItPnR5cGUgPSBJTlRF TF9PVVRQVVRfRFNJOwogCWludGVsX2VuY29kZXItPmNsb25lYWJsZSA9IDA7CiAJZHJtX2Nvbm5l Y3Rvcl9pbml0KGRldiwgY29ubmVjdG9yLCAmaW50ZWxfZHNpX2Nvbm5lY3Rvcl9mdW5jcywKZGlm ZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RzaS5oIGIvZHJpdmVycy9ncHUv ZHJtL2k5MTUvaW50ZWxfZHNpLmgKaW5kZXggMjc4NGFjNC4uYmYxYmFkZSAxMDA2NDQKLS0tIGEv ZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50ZWxfZHNpLmgKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5 MTUvaW50ZWxfZHNpLmgKQEAgLTI5LDYgKzI5LDkgQEAKICNpbmNsdWRlIDxkcm0vZHJtX21pcGlf ZHNpLmg+CiAjaW5jbHVkZSAiaW50ZWxfZHJ2LmgiCiAKKyNkZWZpbmUgUFBTX0JMQ19QTUlDICAg MAorI2RlZmluZSBQUFNfQkxDX1NPQyAgICAxCisKIC8qIER1YWwgTGluayBzdXBwb3J0ICovCiAj ZGVmaW5lIERTSV9EVUFMX0xJTktfTk9ORQkJMAogI2RlZmluZSBEU0lfRFVBTF9MSU5LX0ZST05U X0JBQ0sJMQpAQCAtNDIsNiArNDUsOSBAQCBzdHJ1Y3QgaW50ZWxfZHNpIHsKIAlzdHJ1Y3QgZHJt X3BhbmVsICpwYW5lbDsKIAlzdHJ1Y3QgaW50ZWxfZHNpX2hvc3QgKmRzaV9ob3N0c1tJOTE1X01B WF9QT1JUU107CiAKKwkvKiBHUElPIERlc2MgZm9yIENSQyBiYXNlZCBQYW5lbCBjb250cm9sICov CisJc3RydWN0IGdwaW9fZGVzYyAqZ3Bpb19wYW5lbDsKKwogCXN0cnVjdCBpbnRlbF9jb25uZWN0 b3IgKmF0dGFjaGVkX2Nvbm5lY3RvcjsKIAogCS8qIGJpdCBtYXNrIG9mIHBvcnRzIGJlaW5nIGRy aXZlbiAqLwotLSAKMi4xLjAKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNr dG9wLm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50 ZWwtZ2Z4Cg==