From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756445AbbEUNaT (ORCPT ); Thu, 21 May 2015 09:30:19 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:44669 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1755982AbbEUN3j (ORCPT ); Thu, 21 May 2015 09:29:39 -0400 X-Listener-Flag: 11101 From: YH Huang To: Matthias Brugger , Mark Rutland , Thierry Reding CC: Rob Herring , Pawel Moll , , , , , , , Sascha Hauer , YH Huang Subject: [PATCH v2 1/2] dt-bindings: pwm: add MediaTek display PWM bindings Date: Thu, 21 May 2015 21:29:23 +0800 Message-ID: <1432214964-40644-2-git-send-email-yh.huang@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1432214964-40644-1-git-send-email-yh.huang@mediatek.com> References: <1432214964-40644-1-git-send-email-yh.huang@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the device-tree binding of MediatTek display PWM. Signed-off-by: YH Huang --- .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt new file mode 100644 index 0000000..f55bf92 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -0,0 +1,25 @@ +MediaTek display PWM controller + +Required properties: + - compatible: should be "mediatek,-disp-pwm" + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC + - reg: physical base address and length of the controller's registers + - #pwm-cells: must be 2. See pwm.txt in this directory + for a description of the cell format + - clocks: phandle and clock specifier of the PWM reference clock + - clock-names: must contain the following + - "main": clock used to generate PWM signals + - "mm": sync signals from the modules of mmsys + +Example: + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys MM_DISP_PWM026M>, + <&mmsys MM_DISP_PWM0MM>; + clock-names = "main", + "mm"; + }; -- 1.8.1.1.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: YH Huang Subject: [PATCH v2 1/2] dt-bindings: pwm: add MediaTek display PWM bindings Date: Thu, 21 May 2015 21:29:23 +0800 Message-ID: <1432214964-40644-2-git-send-email-yh.huang@mediatek.com> References: <1432214964-40644-1-git-send-email-yh.huang@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1432214964-40644-1-git-send-email-yh.huang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Matthias Brugger , Mark Rutland , Thierry Reding Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, YH Huang , srv_heupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Pawel Moll , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring , linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Sascha Hauer , linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-mediatek@lists.infradead.org Document the device-tree binding of MediatTek display PWM. Signed-off-by: YH Huang --- .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt new file mode 100644 index 0000000..f55bf92 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -0,0 +1,25 @@ +MediaTek display PWM controller + +Required properties: + - compatible: should be "mediatek,-disp-pwm" + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC + - reg: physical base address and length of the controller's registers + - #pwm-cells: must be 2. See pwm.txt in this directory + for a description of the cell format + - clocks: phandle and clock specifier of the PWM reference clock + - clock-names: must contain the following + - "main": clock used to generate PWM signals + - "mm": sync signals from the modules of mmsys + +Example: + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys MM_DISP_PWM026M>, + <&mmsys MM_DISP_PWM0MM>; + clock-names = "main", + "mm"; + }; -- 1.8.1.1.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: yh.huang@mediatek.com (YH Huang) Date: Thu, 21 May 2015 21:29:23 +0800 Subject: [PATCH v2 1/2] dt-bindings: pwm: add MediaTek display PWM bindings In-Reply-To: <1432214964-40644-1-git-send-email-yh.huang@mediatek.com> References: <1432214964-40644-1-git-send-email-yh.huang@mediatek.com> Message-ID: <1432214964-40644-2-git-send-email-yh.huang@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Document the device-tree binding of MediatTek display PWM. Signed-off-by: YH Huang --- .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt new file mode 100644 index 0000000..f55bf92 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt @@ -0,0 +1,25 @@ +MediaTek display PWM controller + +Required properties: + - compatible: should be "mediatek,-disp-pwm" + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC + - reg: physical base address and length of the controller's registers + - #pwm-cells: must be 2. See pwm.txt in this directory + for a description of the cell format + - clocks: phandle and clock specifier of the PWM reference clock + - clock-names: must contain the following + - "main": clock used to generate PWM signals + - "mm": sync signals from the modules of mmsys + +Example: + pwm0: pwm at 1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys MM_DISP_PWM026M>, + <&mmsys MM_DISP_PWM0MM>; + clock-names = "main", + "mm"; + }; -- 1.8.1.1.dirty