From: Dave Gordon <david.s.gordon@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "Michael H. Nguyen" <michael.h.nguyen@intel.com>
Subject: [PATCH 08/15] drm/i915: Move execlists defines from .c to .h
Date: Mon, 15 Jun 2015 19:36:26 +0100 [thread overview]
Message-ID: <1434393394-21002-9-git-send-email-david.s.gordon@intel.com> (raw)
In-Reply-To: <1434393394-21002-1-git-send-email-david.s.gordon@intel.com>
From: "Michael H. Nguyen" <michael.h.nguyen@intel.com>
Move defines from intel_lrc.c to i915_reg.h so they are accessible
to the GuC submission code; and expose a previously static function
in the execlist code which will also be required for GuC submission.
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen <michael.h.nguyen@intel.com>
Signed-off-by: Alex Dai <yu.dai@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 77 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_lrc.c | 80 +-------------------------------------
drivers/gpu/drm/i915/intel_lrc.h | 2 +
3 files changed, 81 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e4589e..56f81de 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7833,4 +7833,81 @@ enum skl_disp_power_wells {
#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
+/* Exec Lists */
+#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
+#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
+
+#define RING_EXECLIST_QFULL (1 << 0x2)
+#define RING_EXECLIST1_VALID (1 << 0x3)
+#define RING_EXECLIST0_VALID (1 << 0x4)
+#define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
+#define RING_EXECLIST1_ACTIVE (1 << 0x11)
+#define RING_EXECLIST0_ACTIVE (1 << 0x12)
+
+#define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
+#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
+#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
+#define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
+#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
+#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
+
+#define CTX_LRI_HEADER_0 0x01
+#define CTX_CONTEXT_CONTROL 0x02
+#define CTX_RING_HEAD 0x04
+#define CTX_RING_TAIL 0x06
+#define CTX_RING_BUFFER_START 0x08
+#define CTX_RING_BUFFER_CONTROL 0x0a
+#define CTX_BB_HEAD_U 0x0c
+#define CTX_BB_HEAD_L 0x0e
+#define CTX_BB_STATE 0x10
+#define CTX_SECOND_BB_HEAD_U 0x12
+#define CTX_SECOND_BB_HEAD_L 0x14
+#define CTX_SECOND_BB_STATE 0x16
+#define CTX_BB_PER_CTX_PTR 0x18
+#define CTX_RCS_INDIRECT_CTX 0x1a
+#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
+#define CTX_LRI_HEADER_1 0x21
+#define CTX_CTX_TIMESTAMP 0x22
+#define CTX_PDP3_UDW 0x24
+#define CTX_PDP3_LDW 0x26
+#define CTX_PDP2_UDW 0x28
+#define CTX_PDP2_LDW 0x2a
+#define CTX_PDP1_UDW 0x2c
+#define CTX_PDP1_LDW 0x2e
+#define CTX_PDP0_UDW 0x30
+#define CTX_PDP0_LDW 0x32
+#define CTX_LRI_HEADER_2 0x41
+#define CTX_R_PWR_CLK_STATE 0x42
+#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
+
+#define GEN8_CTX_VALID (1<<0)
+#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
+#define GEN8_CTX_FORCE_RESTORE (1<<2)
+#define GEN8_CTX_L3LLC_COHERENT (1<<5)
+#define GEN8_CTX_PRIVILEGE (1<<8)
+
+#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
+ const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
+ ppgtt->pdp.page_directory[n]->daddr : \
+ ppgtt->scratch_pd->daddr; \
+ reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
+ reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
+}
+
+enum {
+ ADVANCED_CONTEXT = 0,
+ LEGACY_CONTEXT,
+ ADVANCED_AD_CONTEXT,
+ LEGACY_64B_CONTEXT
+};
+#define GEN8_CTX_MODE_SHIFT 3
+enum {
+ FAULT_AND_HANG = 0,
+ FAULT_AND_HALT, /* Debug only */
+ FAULT_AND_STREAM,
+ FAULT_AND_CONTINUE /* Unsupported */
+};
+#define GEN8_CTX_ID_SHIFT 32
+
#endif /* _I915_REG_H_ */
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index d5cfab3..4fd1941 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -136,82 +136,6 @@
#include <drm/i915_drm.h>
#include "i915_drv.h"
-#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
-#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
-#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
-
-#define RING_EXECLIST_QFULL (1 << 0x2)
-#define RING_EXECLIST1_VALID (1 << 0x3)
-#define RING_EXECLIST0_VALID (1 << 0x4)
-#define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
-#define RING_EXECLIST1_ACTIVE (1 << 0x11)
-#define RING_EXECLIST0_ACTIVE (1 << 0x12)
-
-#define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
-#define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
-#define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
-#define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
-#define GEN8_CTX_STATUS_COMPLETE (1 << 4)
-#define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
-
-#define CTX_LRI_HEADER_0 0x01
-#define CTX_CONTEXT_CONTROL 0x02
-#define CTX_RING_HEAD 0x04
-#define CTX_RING_TAIL 0x06
-#define CTX_RING_BUFFER_START 0x08
-#define CTX_RING_BUFFER_CONTROL 0x0a
-#define CTX_BB_HEAD_U 0x0c
-#define CTX_BB_HEAD_L 0x0e
-#define CTX_BB_STATE 0x10
-#define CTX_SECOND_BB_HEAD_U 0x12
-#define CTX_SECOND_BB_HEAD_L 0x14
-#define CTX_SECOND_BB_STATE 0x16
-#define CTX_BB_PER_CTX_PTR 0x18
-#define CTX_RCS_INDIRECT_CTX 0x1a
-#define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c
-#define CTX_LRI_HEADER_1 0x21
-#define CTX_CTX_TIMESTAMP 0x22
-#define CTX_PDP3_UDW 0x24
-#define CTX_PDP3_LDW 0x26
-#define CTX_PDP2_UDW 0x28
-#define CTX_PDP2_LDW 0x2a
-#define CTX_PDP1_UDW 0x2c
-#define CTX_PDP1_LDW 0x2e
-#define CTX_PDP0_UDW 0x30
-#define CTX_PDP0_LDW 0x32
-#define CTX_LRI_HEADER_2 0x41
-#define CTX_R_PWR_CLK_STATE 0x42
-#define CTX_GPGPU_CSR_BASE_ADDRESS 0x44
-
-#define GEN8_CTX_VALID (1<<0)
-#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
-#define GEN8_CTX_FORCE_RESTORE (1<<2)
-#define GEN8_CTX_L3LLC_COHERENT (1<<5)
-#define GEN8_CTX_PRIVILEGE (1<<8)
-
-#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \
- const u64 _addr = test_bit(n, ppgtt->pdp.used_pdpes) ? \
- ppgtt->pdp.page_directory[n]->daddr : \
- ppgtt->scratch_pd->daddr; \
- reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
- reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
-}
-
-enum {
- ADVANCED_CONTEXT = 0,
- LEGACY_CONTEXT,
- ADVANCED_AD_CONTEXT,
- LEGACY_64B_CONTEXT
-};
-#define GEN8_CTX_MODE_SHIFT 3
-enum {
- FAULT_AND_HANG = 0,
- FAULT_AND_HALT, /* Debug only */
- FAULT_AND_STREAM,
- FAULT_AND_CONTINUE /* Unsupported */
-};
-#define GEN8_CTX_ID_SHIFT 32
-
static int intel_lr_context_pin(struct intel_engine_cs *ring,
struct intel_context *ctx);
@@ -263,8 +187,8 @@ u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj)
return lrca >> 12;
}
-static uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
- struct drm_i915_gem_object *ctx_obj)
+uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
+ struct drm_i915_gem_object *ctx_obj)
{
struct drm_device *dev = ring->dev;
uint64_t desc;
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 04d3a6d..19c9a02 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -85,6 +85,8 @@ int intel_execlists_submission(struct drm_device *dev, struct drm_file *file,
struct drm_i915_gem_object *batch_obj,
u64 exec_start, u32 dispatch_flags);
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
+uint64_t execlists_ctx_descriptor(struct intel_engine_cs *ring,
+ struct drm_i915_gem_object *ctx_obj);
void intel_lrc_irq_handler(struct intel_engine_cs *ring);
void intel_execlists_retire_requests(struct intel_engine_cs *ring);
--
1.7.9.5
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next prev parent reply other threads:[~2015-06-15 18:38 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-15 18:36 [PATCH 00/15] Batch submission via GuC Dave Gordon
2015-06-15 18:36 ` [PATCH 01/15] drm/i915: Add i915_gem_object_write() to i915_gem.c Dave Gordon
2015-06-15 20:09 ` Chris Wilson
2015-06-17 7:23 ` Dave Gordon
2015-06-17 12:02 ` Daniel Vetter
2015-06-18 11:49 ` Dave Gordon
2015-06-18 12:10 ` Chris Wilson
2015-06-18 18:07 ` Dave Gordon
2015-06-19 8:44 ` Chris Wilson
2015-06-22 11:59 ` Dave Gordon
2015-06-22 12:37 ` Chris Wilson
2015-06-23 16:54 ` Dave Gordon
2015-06-18 14:31 ` Daniel Vetter
2015-06-18 18:28 ` Dave Gordon
2015-06-24 9:32 ` Daniel Vetter
2015-06-25 12:28 ` Dave Gordon
2015-06-24 9:40 ` Chris Wilson
2015-06-15 18:36 ` [PATCH 02/15] drm/i915: Embedded microcontroller (uC) firmware loading support Dave Gordon
2015-06-17 12:05 ` Daniel Vetter
2015-06-18 12:11 ` Dave Gordon
2015-06-18 14:49 ` Daniel Vetter
2015-06-18 15:27 ` Chris Wilson
2015-06-18 15:35 ` Daniel Vetter
2015-06-18 15:49 ` Chris Wilson
2015-06-19 8:43 ` Dave Gordon
2015-06-24 10:29 ` Daniel Vetter
2015-07-06 12:44 ` Dave Gordon
2015-07-06 13:24 ` Daniel Vetter
2015-06-15 18:36 ` [PATCH 03/15] drm/i915: Add GuC-related module parameters Dave Gordon
2015-06-15 18:36 ` [PATCH 04/15] drm/i915: Add GuC-related header files Dave Gordon
2015-06-15 20:20 ` Chris Wilson
2015-06-17 15:01 ` Dave Gordon
2015-06-23 18:10 ` Dave Gordon
2015-06-24 7:41 ` Dave Gordon
2015-06-24 9:37 ` Daniel Vetter
2015-06-15 18:36 ` [PATCH 05/15] drm/i915: GuC-specific firmware loader Dave Gordon
2015-06-15 20:30 ` Chris Wilson
2015-06-18 17:53 ` Yu Dai
2015-06-18 20:12 ` Chris Wilson
2015-06-19 14:34 ` Dave Gordon
2015-06-18 18:54 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 06/15] drm/i915: Debugfs interface to read GuC load status Dave Gordon
2015-06-16 9:40 ` Chris Wilson
2015-06-19 7:49 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 07/15] drm/i915: Defer default hardware context initialisation until first open Dave Gordon
2015-06-16 9:35 ` Chris Wilson
2015-06-19 9:42 ` Dave Gordon
2015-06-17 12:18 ` Daniel Vetter
2015-06-19 9:19 ` Dave Gordon
2015-06-24 10:15 ` Daniel Vetter
2015-06-15 18:36 ` Dave Gordon [this message]
2015-06-16 9:37 ` [PATCH 08/15] drm/i915: Move execlists defines from .c to .h Chris Wilson
2015-06-17 7:31 ` Dave Gordon
2015-06-17 7:54 ` Chris Wilson
2015-06-17 7:59 ` Chris Wilson
2015-06-22 13:05 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 09/15] drm/i915: GuC submission setup, phase 1 Dave Gordon
2015-06-15 21:32 ` Chris Wilson
2015-06-19 17:02 ` Dave Gordon
2015-06-19 17:22 ` Dave Gordon
2015-06-16 11:44 ` Chris Wilson
2015-06-15 18:36 ` [PATCH 10/15] drm/i915: Enable GuC firmware log Dave Gordon
2015-06-15 21:40 ` Chris Wilson
2015-06-16 9:26 ` Tvrtko Ursulin
2015-06-16 11:40 ` Chris Wilson
2015-06-16 12:29 ` Tvrtko Ursulin
2015-06-15 18:36 ` [PATCH 11/15] drm/i915: Implementation of GuC client Dave Gordon
2015-06-15 21:55 ` Chris Wilson
2015-06-19 17:55 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 12/15] drm/i915: Interrupt routing for GuC submission Dave Gordon
2015-06-16 9:24 ` Chris Wilson
2015-06-17 8:20 ` Dave Gordon
2015-06-17 12:22 ` Daniel Vetter
2015-06-17 12:41 ` Daniel Vetter
2015-06-23 11:33 ` Dave Gordon
2015-06-23 23:48 ` Yu Dai
2015-06-24 10:02 ` Daniel Vetter
2015-06-15 18:36 ` [PATCH 13/15] drm/i915: Integrate GuC-based command submission Dave Gordon
2015-06-16 9:22 ` Chris Wilson
2015-06-19 18:18 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 14/15] drm/i915: Debugfs interface for GuC submission statistics Dave Gordon
2015-06-16 9:28 ` Chris Wilson
2015-06-24 8:27 ` Dave Gordon
2015-06-15 18:36 ` [PATCH 15/15] Documentation/drm: kerneldoc for GuC Dave Gordon
2015-06-15 18:36 ` [PATCH 16/15] drm/i915: Enable GuC submission, where supported Dave Gordon
2015-06-17 12:43 ` [PATCH 00/15] Batch submission via GuC Daniel Vetter
2015-06-25 7:23 ` Dave Gordon
2015-06-25 8:05 ` Chris Wilson
2015-06-24 12:16 ` Daniel Vetter
2015-06-24 12:57 ` Chris Wilson
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