From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41340) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4r3g-0003YQ-CO for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z4r3b-0006MF-9d for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:44 -0400 Received: from mail-qk0-x236.google.com ([2607:f8b0:400d:c09::236]:33024) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z4r3b-0006Lj-5P for qemu-devel@nongnu.org; Tue, 16 Jun 2015 09:37:39 -0400 Received: by qkhu186 with SMTP id u186so8788916qkh.0 for ; Tue, 16 Jun 2015 06:37:38 -0700 (PDT) From: "Aurelio C. Remonda" Date: Tue, 16 Jun 2015 10:37:30 -0300 Message-Id: <1434461850-4104-1-git-send-email-aurelioremonda@gmail.com> Subject: [Qemu-devel] [PATCH V4] Target-arm: Add the Cortex-M4 CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, ilg@livius.net, peter.maydell@linaro.org, martin.galvan@tallertechnologies.com, daniel.gutson@tallertechnologies.com This patch adds the Cortex-M4 CPU. The M4 is basically the same as the M3, the main differences being the DSP instructions and an optional FPU. Created an ARM_FEATURE_THUMB_DSP to be added to any non-M thumb2-compatible CPU that uses DSP instructions, and manually added it to the M4 in its initfn. The THUMB_DSP feature was created in a different patch along with the bit checking on each DSP instruction. Only no-FPU cortex-M4 is implemented here, cortex-M4F is not because the core target-arm code doesn't support the M-profile FPU model yet. Signed-off-by: Aurelio C. Remonda --- * Changes in V4: Commit message updated. Deleted unnecessary comment and added a blank line in cortex-M4 initfn. target-arm/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 4a888ab..d25a500 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -783,6 +783,15 @@ static void cortex_m3_initfn(Object *obj) cpu->midr = 0x410fc231; } +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr = 0x410fc240; /* r0p0 */ +} static void arm_v7m_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); @@ -1185,6 +1194,8 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "arm11mpcore", .initfn = arm11mpcore_initfn }, { .name = "cortex-m3", .initfn = cortex_m3_initfn, .class_init = arm_v7m_class_init }, + { .name = "cortex-m4", .initfn = cortex_m4_initfn, + .class_init = arm_v7m_class_init }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn }, { .name = "cortex-a15", .initfn = cortex_a15_initfn }, -- 1.9.1