From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756780AbbFRSDC (ORCPT ); Thu, 18 Jun 2015 14:03:02 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:44582 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756151AbbFRSB3 (ORCPT ); Thu, 18 Jun 2015 14:01:29 -0400 X-Listener-Flag: 11101 From: Scott Shu To: , , , , , , , , , , CC: , , , , Scott Shu Subject: [RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform Date: Fri, 19 Jun 2015 02:01:16 +0800 Message-ID: <1434650481-39421-2-git-send-email-scott.shu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1434650481-39421-1-git-send-email-scott.shu@mediatek.com> References: <1434650481-39421-1-git-send-email-scott.shu@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-MTK: N Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For MT6580 SoC platform, the secondary cores are in powered off state as default, so compared with MT65xx series SoC, one new enable method is needed. This method using the SPM (System Power Manager) inside the SCYSYS to control the CPU power. --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index ac2903d..fb80b2e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6580-smp" "mediatek,mt65xx-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" -- 1.8.1.1.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: Scott Shu Subject: [RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform Date: Fri, 19 Jun 2015 02:01:16 +0800 Message-ID: <1434650481-39421-2-git-send-email-scott.shu@mediatek.com> References: <1434650481-39421-1-git-send-email-scott.shu@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1434650481-39421-1-git-send-email-scott.shu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+glpam-linux-mediatek=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, matthias.bgg-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, rchintakuntla-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org, lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org, marc.ceeeee-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org, catalin.marinas-5wv7dgnIgG8@public.gmane.org, arnd-r2nGTMty4D4@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org Cc: srv_wsdupstream-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org, Scott Shu , linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-mediatek@lists.infradead.org For MT6580 SoC platform, the secondary cores are in powered off state as default, so compared with MT65xx series SoC, one new enable method is needed. This method using the SPM (System Power Manager) inside the SCYSYS to control the CPU power. --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index ac2903d..fb80b2e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6580-smp" "mediatek,mt65xx-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" -- 1.8.1.1.dirty From mboxrd@z Thu Jan 1 00:00:00 1970 From: scott.shu@mediatek.com (Scott Shu) Date: Fri, 19 Jun 2015 02:01:16 +0800 Subject: [RESEND PATCH 1/6] Document: bindings: DT: Add SMP enable method for MT6580 SoC platform In-Reply-To: <1434650481-39421-1-git-send-email-scott.shu@mediatek.com> References: <1434650481-39421-1-git-send-email-scott.shu@mediatek.com> Message-ID: <1434650481-39421-2-git-send-email-scott.shu@mediatek.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org For MT6580 SoC platform, the secondary cores are in powered off state as default, so compared with MT65xx series SoC, one new enable method is needed. This method using the SPM (System Power Manager) inside the SCYSYS to control the CPU power. --- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt index ac2903d..fb80b2e 100644 --- a/Documentation/devicetree/bindings/arm/cpus.txt +++ b/Documentation/devicetree/bindings/arm/cpus.txt @@ -194,6 +194,7 @@ nodes to be present and contain the properties described below. "marvell,armada-380-smp" "marvell,armada-390-smp" "marvell,armada-xp-smp" + "mediatek,mt6580-smp" "mediatek,mt65xx-smp" "mediatek,mt81xx-tz-smp" "qcom,gcc-msm8660" -- 1.8.1.1.dirty