From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34152) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wZY-0001GT-VJ for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5wZT-0006zX-IM for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:08 -0400 Received: from nskntmtas01p.mx.bigpond.com ([61.9.168.137]:65522) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wZT-0006yw-5p for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:43:03 -0400 From: gerg@uclinux.org Date: Fri, 19 Jun 2015 23:43:24 +1000 Message-Id: <1434721406-25288-2-git-send-email-gerg@uclinux.org> In-Reply-To: <1434721406-25288-1-git-send-email-gerg@uclinux.org> References: <1434721406-25288-1-git-send-email-gerg@uclinux.org> Subject: [Qemu-devel] [PATCH v2 1/3] m68k: implement more ColdFire 5208 interrupt controller functionality List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Greg Ungerer From: Greg Ungerer Implement the SIMR and CIMR registers of the 5208 interrupt controller. These are used by modern versions of Linux running on ColdFire (not sure of the exact version they were introduced, but they have been in for quite a while now). Without this change when attempting to run a linux-3.5 kernel you will see: qemu: hardware error: mcf_intc_write: Bad write offset 28 and execution will stop and dump out. Signed-off-by: Greg Ungerer Reviewed-by: Peter Crosthwaite --- hw/m68k/mcf_intc.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index 621423c..f13c7f3 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -102,6 +102,20 @@ static void mcf_intc_write(void *opaque, hwaddr addr, case 0x0c: s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; break; + case 0x1c: + if (val & 0x40) { + s->imr = ~0ull; + } else { + s->imr |= (0x1ull << (val & 0x3f)); + } + break; + case 0x1d: + if (val & 0x40) { + s->imr = 0ull; + } else { + s->imr &= ~(0x1ull << (val & 0x3f)); + } + break; default: hw_error("mcf_intc_write: Bad write offset %d\n", offset); break; -- 1.9.1