From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wdc-0006Gp-Qb for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5wdb-0001Iq-4v for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:20 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:34490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5wda-0001Hr-Tk for qemu-devel@nongnu.org; Fri, 19 Jun 2015 09:47:19 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Z5wdY-0006cF-VM for qemu-devel@nongnu.org; Fri, 19 Jun 2015 14:47:16 +0100 From: Peter Maydell Date: Fri, 19 Jun 2015 14:47:14 +0100 Message-Id: <1434721636-25357-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org> References: <1434721636-25357-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 10/12] arm: xlnx-zynqmp: Add 2xCortexR5 CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Peter Crosthwaite Add the 2xCortexR5 CPUs to zynqmp board. They are powered off on reset (this is true of real hardware) by default or selectable as the boot processor. Signed-off-by: Peter Crosthwaite Message-id: da34128c73ca13fc4f8c3293e1a33d1e1e345655.1434501320.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 2 ++ 2 files changed, 36 insertions(+) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 0c966da..5e72078 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -71,6 +71,13 @@ static void xlnx_zynqmp_init(Object *obj) &error_abort); } + for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { + object_initialize(&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]), + "cortex-r5-" TYPE_ARM_CPU); + object_property_add_child(obj, "rpu-cpu[*]", OBJECT(&s->rpu_cpu[i]), + &error_abort); + } + object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); @@ -163,6 +170,33 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); } + for (i = 0; i < XLNX_ZYNQMP_NUM_RPU_CPUS; i++) { + char *name; + + name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i])); + if (strcmp(name, boot_cpu)) { + /* Secondary CPUs start in PSCI powered-down state */ + object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, + "start-powered-off", &error_abort); + } else { + s->boot_cpu_ptr = &s->rpu_cpu[i]; + } + + object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "reset-hivecs", + &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + + object_property_set_bool(OBJECT(&s->rpu_cpu[i]), true, "realized", + &err); + if (err) { + error_propagate((errp), (err)); + return; + } + } + if (!s->boot_cpu_ptr) { error_setg(errp, "ZynqMP Boot cpu %s not found\n", boot_cpu); return; diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 4f14a22..c379632 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -28,6 +28,7 @@ TYPE_XLNX_ZYNQMP) #define XLNX_ZYNQMP_NUM_APU_CPUS 4 +#define XLNX_ZYNQMP_NUM_RPU_CPUS 2 #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 @@ -48,6 +49,7 @@ typedef struct XlnxZynqMPState { /*< public >*/ ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; + ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; GICState gic; MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; -- 1.9.1