From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Stein Date: Sat, 4 Jul 2015 11:48:39 +0200 Subject: [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1 Message-ID: <1436003324-8769-1-git-send-email-alexanders83@web.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This patchset enables dcache support for Raspberry Pi 1. First the cache support code was made similar to existing arm1136 code. The invalidate and flush functions were inprovoed to accept also non-cacheline aligned addresses. This reduces the cacheline size knowledge from generic code. Then rpi mailbox code has now dcache flush for writing the mailbox request and a dcache invalidation for receiving the mailbox answer. Finally the CONFIG_SYS_DCACHE_OFF switch got removed from rpi config. dcache supprt increases the MMC read performance on RPI 1 from 5,4 MiB/s to 12.3 MiB/s. It doesn't seem to have any affect on RPI 2 though. I just get error messages about non-cacheline aligned address upon invalidation. The performance stucks at 1.2 MiB/s. This was tested by the following command: > fatload mmc 0:1 ${kernel_addr_r} zImage Alexander Stein (5): arm1176/cpu: Match cache_flush to arm1136 arm1176/cpu: Add icache and dcache support arm1176/cpu: Align cache flushing addresses to cacheline size arm/mach-bcm283x/mbox: Flush and invalidate dcache when using fw mailbox arm/rpi: Enable dcache arch/arm/cpu/arm1176/cpu.c | 114 +++++++++++++++++++++++++++++++++++++++++-- arch/arm/mach-bcm283x/mbox.c | 6 +++ include/configs/rpi-common.h | 1 - 3 files changed, 116 insertions(+), 5 deletions(-) -- 2.4.5