From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Stein Date: Sat, 4 Jul 2015 11:48:40 +0200 Subject: [U-Boot] [PATCH 1/5] arm1176/cpu: Match cache_flush to arm1136 In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de> References: <1436003324-8769-1-git-send-email-alexanders83@web.de> Message-ID: <1436003324-8769-2-git-send-email-alexanders83@web.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de This is effectively the same code but it also does a clean cache before invalidating and doing a memory barrier. Signed-off-by: Alexander Stein --- arch/arm/cpu/arm1176/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index 2d81651..24b5cc7 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -41,11 +41,13 @@ int cleanup_before_linux (void) return 0; } -/* flush I/D-cache */ -static void cache_flush (void) +static void cache_flush(void) { + unsigned long i = 0; + /* clean entire data cache */ + asm volatile("mcr p15, 0, %0, c7, c10, 0" : : "r" (i)); /* invalidate both caches and flush btb */ - asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c7, 0" : : "r" (i)); /* mem barrier to sync things */ - asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (0)); + asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (i)); } -- 2.4.5