From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexander Stein Date: Sat, 4 Jul 2015 11:48:42 +0200 Subject: [U-Boot] [PATCH 3/5] arm1176/cpu: Align cache flushing addresses to cacheline size In-Reply-To: <1436003324-8769-1-git-send-email-alexanders83@web.de> References: <1436003324-8769-1-git-send-email-alexanders83@web.de> Message-ID: <1436003324-8769-4-git-send-email-alexanders83@web.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de cache flushing addresses must be cacheline size aligned, so mask the start and stop address appropriately. Signed-off-by: Alexander Stein --- arch/arm/cpu/arm1176/cpu.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/arm1176/cpu.c b/arch/arm/cpu/arm1176/cpu.c index 2ff0e25..5ac8e79 100644 --- a/arch/arm/cpu/arm1176/cpu.c +++ b/arch/arm/cpu/arm1176/cpu.c @@ -57,6 +57,7 @@ static void cache_flush(void) #ifndef CONFIG_SYS_CACHELINE_SIZE #define CONFIG_SYS_CACHELINE_SIZE 32 #endif +#define CACHLINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) void invalidate_dcache_all(void) { @@ -88,6 +89,9 @@ static int check_cache_range(unsigned long start, unsigned long stop) void invalidate_dcache_range(unsigned long start, unsigned long stop) { + stop = (stop + CACHLINE_MASK) & ~CACHLINE_MASK; + start &= ~CACHLINE_MASK; + if (!check_cache_range(start, stop)) return; @@ -99,6 +103,9 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) void flush_dcache_range(unsigned long start, unsigned long stop) { + stop = (stop + CACHLINE_MASK) & ~CACHLINE_MASK; + start &= ~CACHLINE_MASK; + if (!check_cache_range(start, stop)) return; -- 2.4.5