From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753893AbbGINCP (ORCPT ); Thu, 9 Jul 2015 09:02:15 -0400 Received: from mail-bn1bon0081.outbound.protection.outlook.com ([157.56.111.81]:47552 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753857AbbGINCK (ORCPT ); Thu, 9 Jul 2015 09:02:10 -0400 Authentication-Results: spf=pass (sender IP is 149.199.60.100) smtp.mailfrom=xilinx.com; vger.kernel.org; dkim=none (message not signed) header.d=none; From: Ranjit Waghmode To: , , , , , , , , , CC: , , , , , , , Ranjit Waghmode Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Date: Thu, 9 Jul 2015 18:14:54 +0530 Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.0.0.1202-21666.003 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1;BN1AFFO11FD051;1:kN8LFk1irnndenqKppYbVB4auAKautxbwfwuAyuj4CzqWiwA26yW61SGfzfWpTgzTJ4yW+P6IdGwvK33ovZrUeei202o5/2F23f3EpbmFlRlhN7rcorlpHFoO0/JwuJ/jeMAGY7w1avou+g75tRexxbZuuOrUm4h1EwoDh6k4wIPkF232fJCQOdNb3e8XKn1kS6nOQglgyXkpM0STE3iJQH0KF9wlz1y/Y5g1ebOW5bQxcTa9rWh/lSPFgV/Qpg5tzMS9MKv1FHrNW2GBhEpuF8saFCcRljz2Gop4fDGqY+q+ZwNciA1sNdx4NvPYKvEPuIVXBj7f4ZDVxZDLSUWNA== X-Forefront-Antispam-Report: CIP:149.199.60.100;CTRY:US;IPV:NLI;EFV:NLI;SFV:NSPM;SFS:(10009020)(6009001)(2980300002)(438002)(199003)(189002)(46386002)(45336002)(50986999)(107886002)(5001960100002)(2950100001)(62966003)(189998001)(77156002)(229853001)(2201001)(46102003)(86362001)(52956003)(92566002)(76176999)(6806004)(48376002)(19580405001)(87936001)(50226001)(50466002)(42186005)(33646002)(5003940100001)(63266004)(36756003)(19580395003)(106466001)(36386004)(5001770100001)(103686003)(107986001)(921003)(1121003)(217873001)(4001430100001)(90966001);DIR:OUT;SFP:1101;SCL:1;SRVR:BN1AFFO11HUB008;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;MLV:sfv;A:1;MX:1;LANG:en; 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Signed-off-by: Ranjit Waghmode --- drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 87b20a5..271fa80 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; * @dma_rx_bytes: Remaining bytes to receive by DMA mode * @dma_addr: DMA address after mapping the kernel buffer * @genfifoentry: Used for storing the genfifoentry instruction. + * @isinstr: To determine whether the transfer is instruction * @mode: Defines the mode in which QSPI is operating */ struct zynqmp_qspi { @@ -170,6 +171,7 @@ struct zynqmp_qspi { u32 dma_rx_bytes; dma_addr_t dma_addr; u32 genfifoentry; + bool isinstr; enum mode_type mode; }; @@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; genfifoentry |= xqspi->genfifobus; + if (qspi->master->flags & SPI_BOTH_FLASH) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + } else { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + if (!is_high) { genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; + xqspi->isinstr = true; } else { genfifoentry |= GQSPI_GENFIFO_CS_HOLD; } @@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + xqspi->isinstr = false; spi_finalize_current_transfer(master); ret = IRQ_HANDLED; } @@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; + if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE)) + genfifoentry |= GQSPI_GENFIFO_STRIPE; + zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); if (xqspi->mode == GQSPI_MODE_DMA) @@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct resource *res; struct device *dev = &pdev->dev; + u32 num_cs; master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) @@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (ret < 0) + master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + master->num_chipselect = num_cs; master->setup = zynqmp_qspi_setup; master->set_cs = zynqmp_qspi_chipselect; -- 2.1.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: ranjit.waghmode@xilinx.com (Ranjit Waghmode) Date: Thu, 9 Jul 2015 18:14:54 +0530 Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org This patch adds support of dual parallel mode configuration for Zynq Ultrascale+ MPSoC GQSPI controller driver. Signed-off-by: Ranjit Waghmode --- drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 87b20a5..271fa80 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; * @dma_rx_bytes: Remaining bytes to receive by DMA mode * @dma_addr: DMA address after mapping the kernel buffer * @genfifoentry: Used for storing the genfifoentry instruction. + * @isinstr: To determine whether the transfer is instruction * @mode: Defines the mode in which QSPI is operating */ struct zynqmp_qspi { @@ -170,6 +171,7 @@ struct zynqmp_qspi { u32 dma_rx_bytes; dma_addr_t dma_addr; u32 genfifoentry; + bool isinstr; enum mode_type mode; }; @@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; genfifoentry |= xqspi->genfifobus; + if (qspi->master->flags & SPI_BOTH_FLASH) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + } else { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + if (!is_high) { genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; + xqspi->isinstr = true; } else { genfifoentry |= GQSPI_GENFIFO_CS_HOLD; } @@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + xqspi->isinstr = false; spi_finalize_current_transfer(master); ret = IRQ_HANDLED; } @@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; + if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE)) + genfifoentry |= GQSPI_GENFIFO_STRIPE; + zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); if (xqspi->mode == GQSPI_MODE_DMA) @@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct resource *res; struct device *dev = &pdev->dev; + u32 num_cs; master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) @@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (ret < 0) + master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + master->num_chipselect = num_cs; master->setup = zynqmp_qspi_setup; master->set_cs = zynqmp_qspi_chipselect; -- 2.1.2 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ranjit Waghmode Subject: [RFC PATCH 1/2] spi: zynqmp: gqspi: add support for dual parallel mode configuration Date: Thu, 9 Jul 2015 18:14:54 +0530 Message-ID: <1436445895-25504-2-git-send-email-ranjit.waghmode@xilinx.com> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: harinik@xilinx.com, Ranjit Waghmode , linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, punnaia@xilinx.com, ran27jit@gmail.com, linux-arm-kernel@lists.infradead.org To: , , , , , , , , , Return-path: In-Reply-To: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: linux-spi.vger.kernel.org This patch adds support of dual parallel mode configuration for Zynq Ultrascale+ MPSoC GQSPI controller driver. Signed-off-by: Ranjit Waghmode --- drivers/spi/spi-zynqmp-gqspi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c index 87b20a5..271fa80 100644 --- a/drivers/spi/spi-zynqmp-gqspi.c +++ b/drivers/spi/spi-zynqmp-gqspi.c @@ -153,6 +153,7 @@ enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; * @dma_rx_bytes: Remaining bytes to receive by DMA mode * @dma_addr: DMA address after mapping the kernel buffer * @genfifoentry: Used for storing the genfifoentry instruction. + * @isinstr: To determine whether the transfer is instruction * @mode: Defines the mode in which QSPI is operating */ struct zynqmp_qspi { @@ -170,6 +171,7 @@ struct zynqmp_qspi { u32 dma_rx_bytes; dma_addr_t dma_addr; u32 genfifoentry; + bool isinstr; enum mode_type mode; }; @@ -404,9 +406,20 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) genfifoentry |= GQSPI_GENFIFO_MODE_SPI; genfifoentry |= xqspi->genfifobus; + if (qspi->master->flags & SPI_BOTH_FLASH) { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_BOTH, + GQSPI_SELECT_FLASH_BUS_BOTH); + } else { + zynqmp_gqspi_selectslave(xqspi, + GQSPI_SELECT_FLASH_CS_LOWER, + GQSPI_SELECT_FLASH_BUS_LOWER); + } + if (!is_high) { genfifoentry |= xqspi->genfifocs; genfifoentry |= GQSPI_GENFIFO_CS_SETUP; + xqspi->isinstr = true; } else { genfifoentry |= GQSPI_GENFIFO_CS_HOLD; } @@ -663,6 +676,7 @@ static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0) && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); + xqspi->isinstr = false; spi_finalize_current_transfer(master); ret = IRQ_HANDLED; } @@ -826,6 +840,9 @@ static int zynqmp_qspi_start_transfer(struct spi_master *master, genfifoentry |= xqspi->genfifocs; genfifoentry |= xqspi->genfifobus; + if ((!xqspi->isinstr) && (master->flags & SPI_DATA_STRIPE)) + genfifoentry |= GQSPI_GENFIFO_STRIPE; + zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry); if (xqspi->mode == GQSPI_MODE_DMA) @@ -982,6 +999,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) struct zynqmp_qspi *xqspi; struct resource *res; struct device *dev = &pdev->dev; + u32 num_cs; master = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); if (!master) @@ -1042,7 +1060,11 @@ static int zynqmp_qspi_probe(struct platform_device *pdev) goto clk_dis_all; } - master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + ret = of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs); + if (ret < 0) + master->num_chipselect = GQSPI_DEFAULT_NUM_CS; + else + master->num_chipselect = num_cs; master->setup = zynqmp_qspi_setup; master->set_cs = zynqmp_qspi_chipselect; -- 2.1.2