From: Chris Packham <judge.packham@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [Resend RFC PATCH v2] mips: Use unsigned int when reading c0 registers
Date: Tue, 14 Jul 2015 22:54:41 +1200 [thread overview]
Message-ID: <1436871282-5602-2-git-send-email-judge.packham@gmail.com> (raw)
In-Reply-To: <1436871282-5602-1-git-send-email-judge.packham@gmail.com>
In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms
started using common the common timer functions which are based around
the fact that many platforms have a 32-bit free running counter register
that can be used see commit 8dfafdd (Introduce common timer functions).
Even MIPS64 has such a 32-bit register (some have an additional 64-bit free
running counter, but that's something for another time).
The problem is that in __read_32bit_c0_register() we read the value from
this register into an _signed_ int and as it's returned up the call
chain to timer_read_counter() it gets assigned to an unsigned long. On a
32-bit system there is no problem. On a 64-bit system odd things happen,
sign extension seems to kick in and all of a sudden if the counter
register happens to have the MSb (i.e. the sign bit) set the negative
int gets sign extended into a very large unsigned long value. This in
turn throws out things from get_ticks() up.
Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to
use "unsigned int res;" instead of "int res;". There seems to be little
reason to treat these register values as signed. They are either
counters (which by definition are unsigned) or are made up of various
bit fields to be interpreted as per the CPU datasheet.
Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
---
Changes in v2:
- Use Rob's current email address
arch/mips/include/asm/mipsregs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 3571e4f..c7a0849 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -594,7 +594,7 @@ do { \
*/
#define __read_32bit_c0_register(source, sel) \
-({ int __res; \
+({ unsigned int __res; \
if (sel == 0) \
__asm__ __volatile__( \
"mfc0\t%0, " #source "\n\t" \
@@ -676,7 +676,7 @@ do { \
* On RM7000/RM9000 these are uses to access cop0 set 1 registers
*/
#define __read_32bit_c0_ctrl_register(source) \
-({ int __res; \
+({ unsigned int __res; \
__asm__ __volatile__( \
"cfc0\t%0, " #source "\n\t" \
: "=r" (__res)); \
--
2.5.0.rc0
next prev parent reply other threads:[~2015-07-14 10:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-07-14 10:54 [U-Boot] [Resend RFC PATCH v2 0/1] MIPS64 timer bug Chris Packham
2015-07-14 10:54 ` Chris Packham [this message]
2015-07-14 19:01 ` [U-Boot] [Resend RFC PATCH v2] mips: Use unsigned int when reading c0 registers Daniel Schwierzeck
2015-07-14 21:12 ` Chris Packham
2015-07-16 0:14 ` Chris Packham
2015-07-18 9:29 ` Daniel Schwierzeck
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