From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752676AbbGPFPf (ORCPT ); Thu, 16 Jul 2015 01:15:35 -0400 Received: from gate.crashing.org ([63.228.1.57]:42639 "EHLO gate.crashing.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750769AbbGPFPd (ORCPT ); Thu, 16 Jul 2015 01:15:33 -0400 Message-ID: <1437023695.28088.29.camel@kernel.crashing.org> Subject: Re: [RFC PATCH v2] memory-barriers: remove smp_mb__after_unlock_lock() From: Benjamin Herrenschmidt To: Michael Ellerman Cc: Will Deacon , "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Paul McKenney , Peter Zijlstra Date: Thu, 16 Jul 2015 15:14:55 +1000 In-Reply-To: <1437023004.28088.27.camel@kernel.crashing.org> References: <1436789704-10086-1-git-send-email-will.deacon@arm.com> <1436826689.3948.233.camel@kernel.crashing.org> <1436929578.10956.3.camel@ellerman.id.au> <20150715104420.GD1005@arm.com> <1437012028.28475.2.camel@ellerman.id.au> <1437023004.28088.27.camel@kernel.crashing.org> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.12.11-0ubuntu3 Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2015-07-16 at 15:03 +1000, Benjamin Herrenschmidt wrote: > On Thu, 2015-07-16 at 12:00 +1000, Michael Ellerman wrote: > > That would fix the problem with smp_mb__after_unlock_lock(), but not > > the original worry we had about loads happening before the SC in lock. > > However I think isync fixes *that* :-) The problem with isync is as you > said, it's not a -memory- barrier per-se, it's an execution barrier / > context synchronizing instruction. The combination stwcx. + bne + isync > however prevents the execution of anything past the isync until the > stwcx has completed and the bne has been "decided", which prevents loads > from leaking into the LL/SC loop. It will also prevent a store in the > lock from being issued before the stwcx. has completed. It does *not* > prevent as far as I can tell another unrelated store before the lock > from leaking into the lock, including the one used to unlock a different > lock. Except that the architecture says: << Because a Store Conditional instruction may com- plete before its store has been performed, a condi- tional Branch instruction that depends on the CR0 value set by a Store Conditional instruction does not order the Store Conditional's store with respect to storage accesses caused by instructions that follow the Branch >> So isync in lock in architecturally incorrect, despite being what the architecture recommends using, yay ! Ben.