From: vijay.kilari@gmail.com
To: Ian.Campbell@citrix.com, julien.grall@citrix.com,
stefano.stabellini@eu.citrix.com, stefano.stabellini@citrix.com,
tim@xen.org, xen-devel@lists.xen.org
Cc: Prasun.Kapoor@caviumnetworks.com,
Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>,
manish.jaggi@caviumnetworks.com, vijay.kilari@gmail.com
Subject: [PATCH v6 21/31] xen/arm: ITS: Add GITS registers emulation
Date: Mon, 31 Aug 2015 16:36:38 +0530 [thread overview]
Message-ID: <1441019208-2764-22-git-send-email-vijay.kilari@gmail.com> (raw)
In-Reply-To: <1441019208-2764-1-git-send-email-vijay.kilari@gmail.com>
From: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Emulate GITS* registers
Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
---
v6: - Removed unrelated code of this patch
- Used vgic_regN_{read,write}
v4: - Removed GICR register emulation
---
xen/arch/arm/vgic-v3-its.c | 337 ++++++++++++++++++++++++++++++++++++++++-
xen/include/asm-arm/gic-its.h | 16 ++
2 files changed, 352 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/vgic-v3-its.c b/xen/arch/arm/vgic-v3-its.c
index 53f2a27..c384ecf 100644
--- a/xen/arch/arm/vgic-v3-its.c
+++ b/xen/arch/arm/vgic-v3-its.c
@@ -35,6 +35,14 @@
//#define DEBUG_ITS
+/* GITS_PIDRn register values for ARM implementations */
+#define GITS_PIDR0_VAL (0x94)
+#define GITS_PIDR1_VAL (0xb4)
+#define GITS_PIDR2_VAL (0x3b)
+#define GITS_PIDR3_VAL (0x00)
+#define GITS_PIDR4_VAL (0x04)
+#define GITS_BASER_INIT_VAL ((1UL << GITS_BASER_TYPE_SHIFT) | \
+ (0x7UL << GITS_BASER_ENTRY_SIZE_SHIFT))
#ifdef DEBUG_ITS
# define DPRINTK(fmt, args...) dprintk(XENLOG_DEBUG, fmt, ##args)
#else
@@ -535,7 +543,7 @@ static int vits_read_virt_cmd(struct vcpu *v, struct vgic_its *vits,
return 0;
}
-int vits_process_cmd(struct vcpu *v, struct vgic_its *vits)
+static int vits_process_cmd(struct vcpu *v, struct vgic_its *vits)
{
its_cmd_block virt_cmd;
@@ -560,6 +568,322 @@ err:
return 0;
}
+static inline void vits_spin_lock(struct vgic_its *vits)
+{
+ spin_lock(&vits->lock);
+}
+
+static inline void vits_spin_unlock(struct vgic_its *vits)
+{
+ spin_unlock(&vits->lock);
+}
+
+static int vgic_v3_gits_mmio_read(struct vcpu *v, mmio_info_t *info)
+{
+ struct vgic_its *vits = v->domain->arch.vgic.vits;
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ uint64_t val = 0;
+ uint32_t gits_reg;
+
+ gits_reg = info->gpa - vits->gits_base;
+ DPRINTK("%pv: vITS: GITS_MMIO_READ offset 0x%"PRIx32"\n", v, gits_reg);
+
+ switch ( gits_reg )
+ {
+ case GITS_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vits_spin_lock(vits);
+ /*
+ * vITS is always quiescent, has no translations in progress and
+ * completed all operations. So set quescent by default.
+ */
+ *r = vgic_reg32_read((vits->ctrl | GITS_CTLR_QUIESCENT), info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_IIDR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GICV3_GICD_IIDR_VAL, info);
+ return 1;
+ case GITS_TYPER:
+ case GITS_TYPER + 4:
+ /*
+ * GITS_TYPER.HCC = max_vcpus + 1 (max collection supported)
+ * GITS_TYPER.Devbits = HW supported Devbits size
+ * GITS_TYPER.IDbits = HW supported IDbits size
+ * GITS_TYPER.PTA = 0 (Target addresses are linear processor numbers)
+ * GITS_TYPER.ITTSize = Size of struct vitt
+ * GITS_TYPER.Physical = 1
+ */
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ val = ((vits_get_max_collections(v->domain) << GITS_TYPER_HCC_SHIFT ) |
+ ((vits_hw.dev_bits - 1) << GITS_TYPER_DEVBITS_SHIFT) |
+ ((vits_hw.eventid_bits - 1) << GITS_TYPER_IDBITS_SHIFT) |
+ ((sizeof(struct vitt) - 1) << GITS_TYPER_ITT_SIZE_SHIFT) |
+ GITS_TYPER_PHYSICAL_LPIS);
+ if ( dabt.size == DABT_DOUBLE_WORD )
+ *r = vgic_reg64_read(val, info);
+ else
+ *r = vgic_reg32_read(val, info);
+ return 1;
+ case 0x0010 ... 0x007c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- read ignored */
+ goto read_as_zero;
+ case GITS_CBASER:
+ case GITS_CBASER + 4:
+ /* Read supports only 32/64-bit access */
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ if ( dabt.size == DABT_DOUBLE_WORD )
+ *r = vgic_reg64_read(vits->cmd_base, info);
+ else
+ *r = vgic_reg32_read(vits->cmd_base, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_CWRITER:
+ /* Read supports only 32/64-bit access */
+ vits_spin_lock(vits);
+ val = vits->cmd_write;
+ vits_spin_unlock(vits);
+ if ( dabt.size == DABT_DOUBLE_WORD )
+ *r = vgic_reg64_read(val, info);
+ else if (dabt.size == DABT_WORD )
+ *r = vgic_reg32_read(val, info);
+ else
+ goto bad_width;
+ return 1;
+ case GITS_CWRITER + 4:
+ /* BITS[63:20] are RES0 */
+ goto read_as_zero_32;
+ case GITS_CREADR:
+ /* Read supports only 32/64-bit access */
+ val = atomic_read(&vits->cmd_read);
+ if ( dabt.size == DABT_DOUBLE_WORD )
+ *r = vgic_reg64_read(val, info);
+ else if (dabt.size == DABT_WORD )
+ *r = vgic_reg32_read(val, info);
+ else
+ goto bad_width;
+ return 1;
+ case GITS_CREADR + 4:
+ /* BITS[63:20] are RES0 */
+ goto read_as_zero_32;
+ case 0x0098 ... 0x009c:
+ case 0x00a0 ... 0x00fc:
+ case 0x0140 ... 0xbffc:
+ /* Reserved -- read ignored */
+ goto read_as_zero;
+ case GITS_BASER0:
+ /* Supports only 64-bit access */
+ if ( dabt.size == DABT_DOUBLE_WORD )
+ {
+ vits_spin_lock(vits);
+ *r = vgic_reg64_read(vits->baser0, info);
+ vits_spin_unlock(vits);
+ }
+ else
+ goto bad_width;
+ return 1;
+ case GITS_BASER1 ... GITS_BASERN:
+ goto read_as_zero;
+ case GITS_PIDR0:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR0_VAL, info);
+ return 1;
+ case GITS_PIDR1:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR1_VAL, info);
+ return 1;
+ case GITS_PIDR2:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR2_VAL, info);
+ return 1;
+ case GITS_PIDR3:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR3_VAL, info);
+ return 1;
+ case GITS_PIDR4:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ *r = vgic_reg32_read(GITS_PIDR4_VAL, info);
+ return 1;
+ case GITS_PIDR5 ... GITS_PIDR7:
+ goto read_as_zero_32;
+ default:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: unhandled read r%"PRId32" offset 0x%#08"PRIx32"\n",
+ v, dabt.reg, gits_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: bad read width %d r%"PRId32" offset 0x%#08"PRIx32"\n",
+ v, dabt.size, dabt.reg, gits_reg);
+ domain_crash_synchronous();
+ return 0;
+
+read_as_zero_32:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+read_as_zero:
+ *r = 0;
+ return 1;
+}
+
+/*
+ * GITS_BASER.Type[58:56], GITS_BASER.Entry_size[55:48]
+ * and GITS_BASER.Shareability[11:10] are read-only,
+ * Here we support only flat table. So GITS_BASER.Indirect[62]
+ * is RAZ/WI.
+ * Mask those fields while emulating GITS_BASER reg.
+ * TODO: Shareability is set to 0x0 (Reserved) which is fixed.
+ * Implementing fixed value for Shareability is deprecated.
+ */
+#define GITS_BASER_MASK (~((0x7UL << GITS_BASER_TYPE_SHIFT) | \
+ (0x1UL << GITS_BASER_INDIRECT_SHIFT) | \
+ (0xffUL << GITS_BASER_ENTRY_SIZE_SHIFT) | \
+ (0x3UL << GITS_BASER_SHAREABILITY_SHIFT)))
+
+static int vgic_v3_gits_mmio_write(struct vcpu *v, mmio_info_t *info)
+{
+ struct vgic_its *vits = v->domain->arch.vgic.vits;
+ struct hsr_dabt dabt = info->dabt;
+ struct cpu_user_regs *regs = guest_cpu_user_regs();
+ register_t *r = select_user_reg(regs, dabt.reg);
+ int ret;
+ uint32_t gits_reg, sz, psz;
+ uint64_t val;
+
+ gits_reg = info->gpa - vits->gits_base;
+
+ DPRINTK("%pv: vITS: GITS_MMIO_WRITE offset 0x%"PRIx32"\n", v, gits_reg);
+ switch ( gits_reg )
+ {
+ case GITS_CTLR:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ vits_spin_lock(vits);
+ vgic_reg32_write(&vits->ctrl, (*r & GITS_CTLR_ENABLE), info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_IIDR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case GITS_TYPER:
+ case GITS_TYPER + 4:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case 0x0010 ... 0x007c:
+ case 0xc000 ... 0xffcc:
+ /* Implementation defined -- write ignored */
+ goto write_ignore;
+ case GITS_CBASER:
+ /* XXX: support 32-bit access */
+ if ( dabt.size != DABT_DOUBLE_WORD )
+ goto bad_width;
+ vits_spin_lock(vits);
+ if ( vits->ctrl & GITS_CTLR_ENABLE )
+ {
+ /* RO -- write ignored */
+ vits_spin_unlock(vits);
+ goto write_ignore;
+ }
+ vgic_reg64_write(&vits->cmd_base, *r, info);
+ val = SZ_4K * ((*r & GITS_BASER_PAGES_MASK_VAL) + 1);
+ vgic_reg64_write(&vits->cmd_qsize, val, info);
+ if ( vits->cmd_base & GITS_BASER_VALID )
+ atomic_set(&vits->cmd_read, 0);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_CWRITER:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ vits_spin_lock(vits);
+ /* Only BITS[19:0] are writable */
+ vgic_reg64_write(&vits->cmd_write, (*r & 0xfffe0), info);
+ ret = 1;
+ /* CWRITER should be within the range */
+ if ( (vits->ctrl & GITS_CTLR_ENABLE) &&
+ (vits->cmd_write < (vits->cmd_qsize & 0xfffe0)) )
+ ret = vits_process_cmd(v, vits);
+ vits_spin_unlock(vits);
+ return ret;
+ case GITS_CWRITER + 4:
+ /* BITS[63:20] are RES0 */
+ goto write_ignore_32;
+ case GITS_CREADR:
+ /* RO -- write ignored */
+ goto write_ignore;
+ case 0x0098 ... 0x009c:
+ case 0x00a0 ... 0x00fc:
+ case 0x0140 ... 0xbffc:
+ /* Reserved -- write ignored */
+ goto write_ignore;
+ case GITS_BASER0:
+ /* Support only 64-bit access */
+ if ( dabt.size != DABT_DOUBLE_WORD )
+ goto bad_width;
+ vits_spin_lock(vits);
+ /* RO -- write ignored if GITS_CTLR.Enable = 1 */
+ if ( vits->ctrl & GITS_CTLR_ENABLE )
+ {
+ vits_spin_unlock(vits);
+ goto write_ignore_64;
+ }
+ val = vits->baser0 | (*r & GITS_BASER_MASK);
+ vgic_reg64_write(&vits->baser0, val, info);
+ val = vits->baser0 & GITS_BASER_PA_MASK;
+ vgic_reg64_write(&vits->dt_ipa, val, info);
+ psz = (vits->baser0 >> GITS_BASER_PAGE_SIZE_SHIFT) &
+ GITS_BASER_PAGE_SIZE_MASK_VAL;
+ if ( psz == GITS_BASER_PAGE_SIZE_4K_VAL )
+ sz = 4;
+ else if ( psz == GITS_BASER_PAGE_SIZE_16K_VAL )
+ sz = 16;
+ else
+ /* 0x11 and 0x10 are treated as 64K size */
+ sz = 64;
+
+ val = (vits->baser0 & GITS_BASER_PAGES_MASK_VAL)
+ * sz * SZ_1K;
+ vgic_reg64_write(&vits->dt_size, val, info);
+ vits_spin_unlock(vits);
+ return 1;
+ case GITS_BASER1 ... GITS_BASERN:
+ if ( !vgic_reg64_check_access(dabt) ) goto bad_width;
+ goto write_ignore;
+ case GITS_PIDR7 ... GITS_PIDR0:
+ /* R0 -- write ignored */
+ goto write_ignore_32;
+ default:
+ dprintk(XENLOG_G_ERR,
+ "%pv vITS: unhandled write r%"PRId32" offset 0x%#08"PRIx32"\n",
+ v, dabt.reg, gits_reg);
+ return 0;
+ }
+
+bad_width:
+ dprintk(XENLOG_G_ERR,
+ "%pv: vITS: bad write width %d r%"PRId32" offset 0x%#08"PRIx32"\n",
+ v, dabt.size, dabt.reg, gits_reg);
+ domain_crash_synchronous();
+ return 0;
+
+write_ignore_64:
+ if ( dabt.size != DABT_DOUBLE_WORD ) goto bad_width;
+ return 1;
+write_ignore_32:
+ if ( dabt.size != DABT_WORD ) goto bad_width;
+ return 1;
+write_ignore:
+ return 1;
+}
+
+
+static const struct mmio_handler_ops vgic_gits_mmio_handler = {
+ .read_handler = vgic_v3_gits_mmio_read,
+ .write_handler = vgic_v3_gits_mmio_write,
+};
+
int vits_domain_init(struct domain *d)
{
struct vgic_its *vits;
@@ -593,6 +917,17 @@ int vits_domain_init(struct domain *d)
for ( i = 0; i < vits_get_max_collections(d); i++ )
vits->collections[i].target_address = ~0UL;
+ vits->baser0 = GITS_BASER_INIT_VAL;
+
+ /*
+ * Only one virtual ITS is provided to domain.
+ * Assign first physical ITS address to Dom0 virtual ITS.
+ */
+ vits->gits_base = vits_hw.phys_base;
+ vits->gits_size = vits_hw.phys_size;
+
+ register_mmio_handler(d, &vgic_gits_mmio_handler, vits->gits_base, SZ_64K);
+
return 0;
}
diff --git a/xen/include/asm-arm/gic-its.h b/xen/include/asm-arm/gic-its.h
index a3d21f7..db1530e 100644
--- a/xen/include/asm-arm/gic-its.h
+++ b/xen/include/asm-arm/gic-its.h
@@ -53,6 +53,8 @@
#define GITS_TYPER_IDBITS(r) ((((r) >> GITS_TYPER_IDBITS_SHIFT) & 0x1f) + 1)
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HCC_SHIFT (24)
+#define GITS_TYPER_PHYSICAL_LPIS (1UL)
+#define GITS_TYPER_ITT_SIZE_SHIFT (4)
#define GITS_CBASER_VALID (1UL << 63)
#define GITS_CBASER_nC (1UL << 59)
@@ -65,6 +67,7 @@
#define GITS_BASER_NR_REGS 8
#define GITS_BASER_VALID (1UL << 63)
+#define GITS_BASER_INDIRECT_SHIFT (62)
#define GITS_BASER_nC (1UL << 59)
#define GITS_BASER_WaWb (5UL << 59)
#define GITS_BASER_TYPE_SHIFT (56)
@@ -80,6 +83,10 @@
#define GITS_BASER_PAGE_SIZE_16K (1UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_64K (2UL << GITS_BASER_PAGE_SIZE_SHIFT)
#define GITS_BASER_PAGE_SIZE_MASK (3UL << GITS_BASER_PAGE_SIZE_SHIFT)
+#define GITS_BASER_PAGE_SIZE_4K_VAL (0)
+#define GITS_BASER_PAGE_SIZE_16K_VAL (1)
+#define GITS_BASER_PAGE_SIZE_MASK_VAL (0x3)
+#define GITS_BASER_PAGES_MASK_VAL (0xff)
#define GITS_BASER_TYPE_NONE 0
#define GITS_BASER_TYPE_DEVICE 1
#define GITS_BASER_TYPE_VCPU 2
@@ -88,6 +95,7 @@
#define GITS_BASER_TYPE_RESERVED5 5
#define GITS_BASER_TYPE_RESERVED6 6
#define GITS_BASER_TYPE_RESERVED7 7
+#define GITS_BASER_PA_MASK (0xfffffffff000UL)
/*
* ITS commands
@@ -124,6 +132,8 @@ struct its_collection {
struct vgic_its
{
spinlock_t lock;
+ /* Emulation of BASER0 */
+ paddr_t baser0;
/* Command queue base */
paddr_t cmd_base;
/* Command queue write pointer */
@@ -132,6 +142,12 @@ struct vgic_its
atomic_t cmd_read;
/* Command queue size */
unsigned long cmd_qsize;
+ /* ITS mmio physical base */
+ paddr_t gits_base;
+ /* ITS mmio physical size */
+ unsigned long gits_size;
+ /* GICR ctrl register */
+ uint32_t ctrl;
/* vITT device table ipa */
paddr_t dt_ipa;
/* vITT device table size */
--
1.7.9.5
next prev parent reply other threads:[~2015-08-31 11:06 UTC|newest]
Thread overview: 87+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-31 11:06 [PATCH v6 00/31] Add ITS support vijay.kilari
2015-08-31 11:06 ` [PATCH v6 01/31] xen/dt: Handle correctly node with interrupt-map in dt_for_each_irq_map vijay.kilari
2015-08-31 14:20 ` Julien Grall
2015-09-02 15:28 ` Ian Campbell
2015-09-02 15:30 ` Wei Liu
2015-09-02 15:45 ` Julien Grall
2015-09-02 15:52 ` Ian Campbell
2015-09-04 14:41 ` Ian Campbell
2015-08-31 11:06 ` [PATCH v6 02/31] xen/arm: Add bitmap_find_next_zero_area helper function vijay.kilari
2015-08-31 11:06 ` [PATCH v6 03/31] xen: Add log2 functionality vijay.kilari
2015-08-31 11:21 ` Jan Beulich
2015-08-31 11:06 ` [PATCH v6 04/31] xen/arm: Set nr_cpu_ids to available number of cpus vijay.kilari
2015-08-31 14:25 ` Julien Grall
2015-09-09 12:48 ` Ian Campbell
2015-08-31 11:06 ` [PATCH v6 05/31] xen/arm: Rename NR_IRQs and vgic_num_irqs helper function vijay.kilari
2015-08-31 14:40 ` Julien Grall
2015-09-09 13:08 ` Ian Campbell
2015-09-09 13:23 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 06/31] xen/arm: ITS: Port ITS driver to Xen vijay.kilari
2015-08-31 15:41 ` Julien Grall
2015-09-03 17:02 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 07/31] xen/arm: ITS: Add helper functions to manage its_devices vijay.kilari
2015-08-31 11:06 ` [PATCH v6 08/31] xen/arm: ITS: Introduce msi_desc for LPIs vijay.kilari
2015-08-31 16:20 ` Julien Grall
2015-09-09 13:16 ` Ian Campbell
2015-09-09 13:28 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 09/31] xen/arm: ITS: Add APIs to add and assign device vijay.kilari
2015-09-03 17:34 ` Julien Grall
2015-09-09 13:28 ` Ian Campbell
2015-09-09 13:44 ` Julien Grall
2015-09-09 15:07 ` Ian Campbell
2015-09-09 16:19 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 10/31] xen/arm: ITS: Introduce gic_is_lpi helper function vijay.kilari
2015-08-31 16:49 ` Julien Grall
2015-09-01 9:02 ` Vijay Kilari
2015-09-01 11:40 ` Julien Grall
2015-09-01 11:56 ` Vijay Kilari
2015-09-01 13:02 ` Julien Grall
2015-09-03 6:32 ` Vijay Kilari
2015-09-03 9:48 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 11/31] xen/arm: ITS: Enable compilation of physical ITS driver vijay.kilari
2015-08-31 11:06 ` [PATCH v6 12/31] xen/arm: Move vgic locking inside get_irq_priority callback vijay.kilari
2015-08-31 16:34 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 13/31] xen/arm: ITS: implement hw_irq_controller for LPIs vijay.kilari
2015-08-31 17:53 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 14/31] xen/arm: ITS: Initialize physical ITS and export lpi support vijay.kilari
2015-08-31 18:35 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 15/31] xen/arm: ITS: Add virtual ITS driver vijay.kilari
2015-09-02 17:20 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 16/31] xen/arm: ITS: Add virtual ITS commands support vijay.kilari
2015-09-03 15:07 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 17/31] xen/arm: ITS: Store LPIs allocated and IRQ ID bits per domain vijay.kilari
2015-09-03 16:25 ` Julien Grall
2015-09-07 6:59 ` Vijay Kilari
2015-09-07 10:56 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 18/31] xen/arm: ITS: Enable virtual ITS driver vijay.kilari
2015-08-31 11:06 ` [PATCH v6 19/31] xen/arm: ITS: Export ITS info to Virtual ITS vijay.kilari
2015-09-03 16:48 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 20/31] xen/arm: ITS: Introduce helper to get number of event IDs vijay.kilari
2015-09-03 17:51 ` Julien Grall
2015-08-31 11:06 ` vijay.kilari [this message]
2015-09-07 13:14 ` [PATCH v6 21/31] xen/arm: ITS: Add GITS registers emulation Julien Grall
2015-08-31 11:06 ` [PATCH v6 22/31] xen/arm: ITS: Add virtual ITS availability check helper vijay.kilari
2015-09-07 13:41 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 23/31] xen/arm: ITS: Add 32-bit access to GICR_TYPER vijay.kilari
2015-08-31 16:06 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 24/31] xen/arm: ITS: Add GICR register emulation vijay.kilari
2015-09-07 14:20 ` Julien Grall
2015-09-07 15:26 ` Vijay Kilari
2015-09-09 13:55 ` Ian Campbell
2015-09-09 16:11 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 25/31] xen/arm: ITS: Allocate irq descriptors for LPIs vijay.kilari
2015-08-31 11:06 ` [PATCH v6 26/31] xen/arm: ITS: Allocate pending_lpi " vijay.kilari
2015-08-31 11:06 ` [PATCH v6 27/31] xen/arm: ITS: Route LPIs vijay.kilari
2015-08-31 11:06 ` [PATCH v6 28/31] xen/arm: ITS: Add domain specific ITS initialization vijay.kilari
2015-08-31 11:06 ` [PATCH v6 29/31] xen/arm: ITS: Map ITS translation space vijay.kilari
2015-08-31 19:07 ` Julien Grall
2015-08-31 11:06 ` [PATCH v6 30/31] xen/arm: ITS: Generate ITS node for Dom0 vijay.kilari
2015-08-31 11:06 ` [PATCH v6 31/31] xen/arm: ITS: Add pci devices in ThunderX vijay.kilari
2015-09-09 15:22 ` Ian Campbell
2015-09-02 15:38 ` [PATCH v6 00/31] Add ITS support Ian Campbell
2015-09-02 15:52 ` Ian Campbell
2015-09-03 16:45 ` Julien Grall
2015-09-09 15:29 ` Ian Campbell
2015-09-14 11:00 ` Vijay Kilari
2015-09-14 11:09 ` Julien Grall
2015-09-14 13:04 ` Vijay Kilari
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