From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37101) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zb3Gb-0002cU-Op for qemu-devel@nongnu.org; Sun, 13 Sep 2015 05:08:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zb3GZ-0000JH-2E for qemu-devel@nongnu.org; Sun, 13 Sep 2015 05:08:09 -0400 Received: from mail-wi0-x22e.google.com ([2a00:1450:400c:c05::22e]:35237) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zb3GY-0000JB-RR for qemu-devel@nongnu.org; Sun, 13 Sep 2015 05:08:06 -0400 Received: by wicge5 with SMTP id ge5so107336327wic.0 for ; Sun, 13 Sep 2015 02:08:06 -0700 (PDT) From: "Edgar E. Iglesias" Date: Sun, 13 Sep 2015 11:07:51 +0200 Message-Id: <1442135278-25281-2-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1442135278-25281-1-git-send-email-edgar.iglesias@gmail.com> References: <1442135278-25281-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 1/8] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Handle missing CPU support for EL3 gracefully. Signed-off-by: Edgar E. Iglesias --- hw/cpu/a15mpcore.c | 2 +- hw/cpu/a9mpcore.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 4ef8db1..94e8cc1 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -64,7 +64,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) * either all the CPUs have TZ, or none do. */ cpuobj = OBJECT(qemu_get_cpu(0)); - has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + has_el3 = object_property_find(cpuobj, "has_el3", NULL) && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); } diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 7046246..869818c 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -69,7 +69,7 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) * either all the CPUs have TZ, or none do. */ cpuobj = OBJECT(qemu_get_cpu(0)); - has_el3 = object_property_find(cpuobj, "has_el3", &error_abort) && + has_el3 = object_property_find(cpuobj, "has_el3", NULL) && object_property_get_bool(cpuobj, "has_el3", &error_abort); qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); -- 1.9.1