From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: edgar.iglesias@xilinx.com, serge.fdrv@gmail.com,
alex.bennee@linaro.org, agraf@suse.de
Subject: [Qemu-devel] [PATCH v2 2/8] target-arm: Add VTCR_EL2
Date: Sun, 13 Sep 2015 11:07:52 +0200 [thread overview]
Message-ID: <1442135278-25281-3-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1442135278-25281-1-git-send-email-edgar.iglesias@gmail.com>
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 43 +++++++++++++++++++++++++++++++++++++++++--
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5abd8ba..f45fd05 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -224,6 +224,7 @@ typedef struct CPUARMState {
};
/* MMU translation table base control. */
TCR tcr_el[4];
+ TCR vtcr_el2; /* Virtualization Translation Control. */
uint32_t c2_data; /* MPU data cacheable bits. */
uint32_t c2_insn; /* MPU instruction cacheable bits. */
union { /* MMU domain access control register
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d453120..c49b954 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -325,6 +325,34 @@ void init_cpreg_list(ARMCPU *cpu)
g_list_free(keys);
}
+/*
+ * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
+ * they are accesible when EL3 is using AArch64 regardless of EL3.NS.
+ *
+ * access_el3_aa32ns: Used to check AArch32 register views.
+ * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
+ */
+static CPAccessResult access_el3_aa32ns(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ bool secure = arm_is_secure_below_el3(env);
+
+ assert(!arm_el_is_aa64(env, 3));
+ if (secure) {
+ return CP_ACCESS_TRAP_UNCATEGORIZED;
+ }
+ return CP_ACCESS_OK;
+}
+
+static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
+ const ARMCPRegInfo *ri)
+{
+ if (!arm_el_is_aa64(env, 3)) {
+ return access_el3_aa32ns(env, ri);
+ }
+ return CP_ACCESS_OK;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
@@ -3112,6 +3140,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
+ .type = ARM_CP_CONST, .resetvalue = 0 },
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
@@ -3246,6 +3278,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.access = PL2_RW, .writefn = vmsa_tcr_el1_write,
.resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
+ { .name = "VTCR", .state = ARM_CP_STATE_AA32,
+ .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
+ .access = PL2_RW, .accessfn = access_el3_aa32ns,
+ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
+ { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
+ .access = PL2_RW, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
@@ -5741,8 +5781,7 @@ static inline bool regime_translation_disabled(CPUARMState *env,
static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
{
if (mmu_idx == ARMMMUIdx_S2NS) {
- /* TODO: return VTCR_EL2 */
- g_assert_not_reached();
+ return &env->cp15.vtcr_el2;
}
return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
}
--
1.9.1
next prev parent reply other threads:[~2015-09-13 9:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-13 9:07 [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 4 Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 1/8] hw/cpu/{a15mpcore, a9mpcore}: Handle missing has_el3 CPU props gracefully Edgar E. Iglesias
2015-09-14 2:13 ` Peter Crosthwaite
2015-09-13 9:07 ` Edgar E. Iglesias [this message]
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 3/8] target-arm: Add VTTBR_EL2 Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 4/8] target-arm: Suppress TBI for S2 translations Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 5/8] target-arm: Suppress EPD for S2, EL2 and EL3 translations Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 6/8] target-arm: Add VPIDR_EL2 Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 7/8] target-arm: Break out mpidr_read_val() Edgar E. Iglesias
2015-09-13 9:07 ` [Qemu-devel] [PATCH v2 8/8] target-arm: Add VMPIDR_EL2 Edgar E. Iglesias
2015-09-14 13:34 ` [Qemu-devel] [PATCH v2 0/8] arm: Steps towards EL2 support round 4 Peter Maydell
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