From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com ([192.55.52.93]:28257 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751245AbbINEz2 (ORCPT ); Mon, 14 Sep 2015 00:55:28 -0400 From: Sivakumar Thulasimani To: intel-gfx@lists.freedesktop.org Cc: "Thulasimani,Sivakumar" , stable@vger.kernel.org, Jani Nikula Subject: [PATCH] Revert "drm/i915: Add eDP intermediate frequencies for CHV" Date: Mon, 14 Sep 2015 10:25:31 +0530 Message-Id: <1442206531-29776-1-git-send-email-sivakumar.thulasimani@intel.com> In-Reply-To: <144201029915714@kroah.com> References: <144201029915714@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org List-ID: From: "Thulasimani,Sivakumar" This reverts commit: fe51bfb95c996733150c44d21e1c9f4b6322a326. Author: Ville Syrjälä Date: Thu Mar 12 17:10:38 2015 +0200 CHV does not support intermediate frequencies so reverting the patch that added it in the first place Cc: stable@vger.kernel.org Reviewed-by: Ville Syrjälä Signed-off-by: Sivakumar Thulasimani Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dp.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index b1fe32b..3e277c4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -87,9 +87,6 @@ static const struct dp_link_dpll chv_dpll[] = { /* Skylake supports following rates */ static const int gen9_rates[] = { 162000, 216000, 270000, 324000, 432000, 540000 }; -static const int chv_rates[] = { 162000, 202500, 210000, 216000, - 243000, 270000, 324000, 405000, - 420000, 432000, 540000 }; static const int default_rates[] = { 162000, 270000, 540000 }; /** @@ -1169,9 +1166,6 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates) if (INTEL_INFO(dev)->gen >= 9) { *source_rates = gen9_rates; return ARRAY_SIZE(gen9_rates); - } else if (IS_CHERRYVIEW(dev)) { - *source_rates = chv_rates; - return ARRAY_SIZE(chv_rates); } *source_rates = default_rates; -- 1.7.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sivakumar Thulasimani Subject: [PATCH] Revert "drm/i915: Add eDP intermediate frequencies for CHV" Date: Mon, 14 Sep 2015 10:25:31 +0530 Message-ID: <1442206531-29776-1-git-send-email-sivakumar.thulasimani@intel.com> References: <144201029915714@kroah.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id DE9526E102 for ; Sun, 13 Sep 2015 21:55:28 -0700 (PDT) In-Reply-To: <144201029915714@kroah.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: intel-gfx@lists.freedesktop.org Cc: Jani Nikula , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org RnJvbTogIlRodWxhc2ltYW5pLFNpdmFrdW1hciIgPHNpdmFrdW1hci50aHVsYXNpbWFuaUBpbnRl bC5jb20+CgpUaGlzIHJldmVydHMKY29tbWl0OiBmZTUxYmZiOTVjOTk2NzMzMTUwYzQ0ZDIxZTFj OWY0YjYzMjJhMzI2LgpBdXRob3I6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFsYUBsaW51 eC5pbnRlbC5jb20+CkRhdGU6ICAgVGh1IE1hciAxMiAxNzoxMDozOCAyMDE1ICswMjAwCgpDSFYg ZG9lcyBub3Qgc3VwcG9ydCBpbnRlcm1lZGlhdGUgZnJlcXVlbmNpZXMgc28gcmV2ZXJ0aW5nIHRo ZQpwYXRjaCB0aGF0IGFkZGVkIGl0IGluIHRoZSBmaXJzdCBwbGFjZQoKQ2M6IHN0YWJsZUB2Z2Vy Lmtlcm5lbC5vcmcKUmV2aWV3ZWQtYnk6IFZpbGxlIFN5cmrDpGzDpCA8dmlsbGUuc3lyamFsYUBs aW51eC5pbnRlbC5jb20+ClNpZ25lZC1vZmYtYnk6IFNpdmFrdW1hciBUaHVsYXNpbWFuaSA8c2l2 YWt1bWFyLnRodWxhc2ltYW5pQGludGVsLmNvbT4KU2lnbmVkLW9mZi1ieTogSmFuaSBOaWt1bGEg PGphbmkubmlrdWxhQGludGVsLmNvbT4KLS0tCiBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pbnRlbF9k cC5jIHwgICAgNiAtLS0tLS0KIDEgZmlsZSBjaGFuZ2VkLCA2IGRlbGV0aW9ucygtKQoKZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwLmMgYi9kcml2ZXJzL2dwdS9kcm0v aTkxNS9pbnRlbF9kcC5jCmluZGV4IGIxZmUzMmIuLjNlMjc3YzQgMTAwNjQ0Ci0tLSBhL2RyaXZl cnMvZ3B1L2RybS9pOTE1L2ludGVsX2RwLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvaW50 ZWxfZHAuYwpAQCAtODcsOSArODcsNiBAQCBzdGF0aWMgY29uc3Qgc3RydWN0IGRwX2xpbmtfZHBs bCBjaHZfZHBsbFtdID0gewogLyogU2t5bGFrZSBzdXBwb3J0cyBmb2xsb3dpbmcgcmF0ZXMgKi8K IHN0YXRpYyBjb25zdCBpbnQgZ2VuOV9yYXRlc1tdID0geyAxNjIwMDAsIDIxNjAwMCwgMjcwMDAw LAogCQkJCSAgMzI0MDAwLCA0MzIwMDAsIDU0MDAwMCB9Owotc3RhdGljIGNvbnN0IGludCBjaHZf cmF0ZXNbXSA9IHsgMTYyMDAwLCAyMDI1MDAsIDIxMDAwMCwgMjE2MDAwLAotCQkJCSAyNDMwMDAs IDI3MDAwMCwgMzI0MDAwLCA0MDUwMDAsCi0JCQkJIDQyMDAwMCwgNDMyMDAwLCA1NDAwMDAgfTsK IHN0YXRpYyBjb25zdCBpbnQgZGVmYXVsdF9yYXRlc1tdID0geyAxNjIwMDAsIDI3MDAwMCwgNTQw MDAwIH07CiAKIC8qKgpAQCAtMTE2OSw5ICsxMTY2LDYgQEAgaW50ZWxfZHBfc291cmNlX3JhdGVz KHN0cnVjdCBkcm1fZGV2aWNlICpkZXYsIGNvbnN0IGludCAqKnNvdXJjZV9yYXRlcykKIAlpZiAo SU5URUxfSU5GTyhkZXYpLT5nZW4gPj0gOSkgewogCQkqc291cmNlX3JhdGVzID0gZ2VuOV9yYXRl czsKIAkJcmV0dXJuIEFSUkFZX1NJWkUoZ2VuOV9yYXRlcyk7Ci0JfSBlbHNlIGlmIChJU19DSEVS UllWSUVXKGRldikpIHsKLQkJKnNvdXJjZV9yYXRlcyA9IGNodl9yYXRlczsKLQkJcmV0dXJuIEFS UkFZX1NJWkUoY2h2X3JhdGVzKTsKIAl9CiAKIAkqc291cmNlX3JhdGVzID0gZGVmYXVsdF9yYXRl czsKLS0gCjEuNy45LjUKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9w Lm9yZwpodHRwOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwt Z2Z4Cg==