From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34898) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTEU-0008Sj-7K for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:51:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbTEP-0002nB-4w for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:51:42 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:64298) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbTEO-0002my-V4 for qemu-devel@nongnu.org; Mon, 14 Sep 2015 08:51:37 -0400 From: Leon Alrae Date: Mon, 14 Sep 2015 13:51:31 +0100 Message-ID: <1442235091-15874-1-git-send-email-leon.alrae@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Implement the relationship between CP0.Status.KX, SX and UX. It should not be possible to set UX bit if SX is 0, the same applies for setting SX if KX is 0. Signed-off-by: Leon Alrae --- target-mips/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 210370e..de8380c 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1003,7 +1003,12 @@ static inline void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) if (env->insn_flags & ISA_MIPS32R6) { bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; - +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { mask &= ~(3 << CP0St_KSU); } -- 2.1.0