From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbUCB-0004hN-Mk for qemu-devel@nongnu.org; Mon, 14 Sep 2015 09:53:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZbUCA-0000DP-KN for qemu-devel@nongnu.org; Mon, 14 Sep 2015 09:53:23 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35073) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZbUCA-00005c-Ep for qemu-devel@nongnu.org; Mon, 14 Sep 2015 09:53:22 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZbUBz-0007tK-Qi for qemu-devel@nongnu.org; Mon, 14 Sep 2015 14:53:11 +0100 From: Peter Maydell Date: Mon, 14 Sep 2015 14:52:58 +0100 Message-Id: <1442238791-30255-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1442238791-30255-1-git-send-email-peter.maydell@linaro.org> References: <1442238791-30255-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Richard Henderson For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) But since the range of bits for !SF are already constrained by unallocated_encoding, we'll never reference the high bits anyway. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 1441909103-24666-10-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f2f8443..3ab0b42 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3015,7 +3015,11 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) } tcg_rd = cpu_reg(s, rd); - tcg_tmp = read_cpu_reg(s, rn, sf); + + /* Suppress the zero-extend for !sf. Since RI and SI are constrained + to be smaller than bitsize, we'll never reference data outside the + low 32-bits anyway. */ + tcg_tmp = read_cpu_reg(s, rn, 1); /* Recognize the common aliases. */ if (opc == 0) { /* SBFM */ -- 1.9.1