From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754752AbbLGIYl (ORCPT ); Mon, 7 Dec 2015 03:24:41 -0500 Received: from szxga02-in.huawei.com ([119.145.14.65]:30949 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754123AbbLGIYi (ORCPT ); Mon, 7 Dec 2015 03:24:38 -0500 From: yankejian To: , , , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v2 next 1/2] dts: hisi: fixes no syscon error when init mdio Date: Mon, 7 Dec 2015 16:25:06 +0800 Message-ID: <1449476707-224320-2-git-send-email-yankejian@huawei.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449476707-224320-1-git-send-email-yankejian@huawei.com> References: <1449476707-224320-1-git-send-email-yankejian@huawei.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.56653ED4.007B,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 6fcfc34ca0a0b7a5338b26be08f7c4ab Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Signed-nux start up, we get the log below: "Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl mdio_bus mdio@803c0000: mdio sys ctl reg has not maped " the source code about the subctrl is dealled with syscon, but dts doesn't. it cause such fault. so this patch adds the syscon info on dts files to fixes it. and it adds documentation for the devicetree bindings used by DT files of Hisilicon Hip05-D02 development board. Signed-off-by: yankejian --- change log: v2: 1) updates the related documented in the binding as well 2) use the normal naming conventions using '-' instead of '_' v1: initial version --- .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 +++++ arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 6ac7c00..9f05767 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -187,6 +187,22 @@ Example: reg = <0xb0000000 0x10000>; }; +Hisilicon HiP05 PERISUB system controller + +Required properties: +- compatible : "hisilicon,peri-c-subctrl", "syscon"; +- reg : Register address and size + +The HiP05 PERISUB system controller is shared by peripheral controllers in +HiP05 Soc to implement some basic configurations. the peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 PCIe-SAS system */ + peri-c-subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; ----------------------------------------------------------------------- Hisilicon CPU controller diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4ff16d0..5fec740 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -246,6 +246,11 @@ clock-frequency = <200000000>; }; + peri_c_subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = < 0x0 0x80000000 0x0 0x10000>; + }; + uart0: uart@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi index 606dd5a..da7b6e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi @@ -10,8 +10,8 @@ soc0: soc@000000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x803c0000 0x0 0x10000 - 0x0 0x80000000 0x0 0x10000>; + reg = <0x0 0x803c0000 0x0 0x10000>; + subctrl-vbase = <&peri_c_subctrl>; soc0_phy0: ethernet-phy@0 { reg = <0x0>; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: yankejian Subject: [PATCH v2 next 1/2] dts: hisi: fixes no syscon error when init mdio Date: Mon, 7 Dec 2015 16:25:06 +0800 Message-ID: <1449476707-224320-2-git-send-email-yankejian@huawei.com> References: <1449476707-224320-1-git-send-email-yankejian@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1449476707-224320-1-git-send-email-yankejian@huawei.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: davem@davemloft.net, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, xuwei5@hisilicon.com, catalin.marinas@arm.com, will.deacon@arm.com, wangkefeng.wang@huawei.com, dingtianhong@huawei.com, liguozhu@huawei.com, Yisen.Zhuang@huawei.com, sboyd@codeaurora.org, haojian.zhuang@linaro.org, wangzhou1@hisilicon.com, bintian.wang@huawei.com, long.wanglong@huawei.com, leo.yan@linaro.org Cc: devicetree@vger.kernel.org, haifeng.wei@huawei.com, netdev@vger.kernel.org, linuxarm@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org Signed-nux start up, we get the log below: "Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl mdio_bus mdio@803c0000: mdio sys ctl reg has not maped " the source code about the subctrl is dealled with syscon, but dts doesn't. it cause such fault. so this patch adds the syscon info on dts files to fixes it. and it adds documentation for the devicetree bindings used by DT files of Hisilicon Hip05-D02 development board. Signed-off-by: yankejian --- change log: v2: 1) updates the related documented in the binding as well 2) use the normal naming conventions using '-' instead of '_' v1: initial version --- .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 +++++ arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 6ac7c00..9f05767 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -187,6 +187,22 @@ Example: reg = <0xb0000000 0x10000>; }; +Hisilicon HiP05 PERISUB system controller + +Required properties: +- compatible : "hisilicon,peri-c-subctrl", "syscon"; +- reg : Register address and size + +The HiP05 PERISUB system controller is shared by peripheral controllers in +HiP05 Soc to implement some basic configurations. the peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 PCIe-SAS system */ + peri-c-subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; ----------------------------------------------------------------------- Hisilicon CPU controller diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4ff16d0..5fec740 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -246,6 +246,11 @@ clock-frequency = <200000000>; }; + peri_c_subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = < 0x0 0x80000000 0x0 0x10000>; + }; + uart0: uart@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi index 606dd5a..da7b6e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi @@ -10,8 +10,8 @@ soc0: soc@000000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x803c0000 0x0 0x10000 - 0x0 0x80000000 0x0 0x10000>; + reg = <0x0 0x803c0000 0x0 0x10000>; + subctrl-vbase = <&peri_c_subctrl>; soc0_phy0: ethernet-phy@0 { reg = <0x0>; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: yankejian Subject: [PATCH v2 next 1/2] dts: hisi: fixes no syscon error when init mdio Date: Mon, 7 Dec 2015 16:25:06 +0800 Message-ID: <1449476707-224320-2-git-send-email-yankejian@huawei.com> References: <1449476707-224320-1-git-send-email-yankejian@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: devicetree@vger.kernel.org, haifeng.wei@huawei.com, netdev@vger.kernel.org, linuxarm@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org To: , , , , , , , , , , , , , , , , , , Return-path: In-Reply-To: <1449476707-224320-1-git-send-email-yankejian@huawei.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: netdev.vger.kernel.org Signed-nux start up, we get the log below: "Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl mdio_bus mdio@803c0000: mdio sys ctl reg has not maped " the source code about the subctrl is dealled with syscon, but dts doesn't. it cause such fault. so this patch adds the syscon info on dts files to fixes it. and it adds documentation for the devicetree bindings used by DT files of Hisilicon Hip05-D02 development board. Signed-off-by: yankejian --- change log: v2: 1) updates the related documented in the binding as well 2) use the normal naming conventions using '-' instead of '_' v1: initial version --- .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 +++++ arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 6ac7c00..9f05767 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -187,6 +187,22 @@ Example: reg = <0xb0000000 0x10000>; }; +Hisilicon HiP05 PERISUB system controller + +Required properties: +- compatible : "hisilicon,peri-c-subctrl", "syscon"; +- reg : Register address and size + +The HiP05 PERISUB system controller is shared by peripheral controllers in +HiP05 Soc to implement some basic configurations. the peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 PCIe-SAS system */ + peri-c-subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; ----------------------------------------------------------------------- Hisilicon CPU controller diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4ff16d0..5fec740 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -246,6 +246,11 @@ clock-frequency = <200000000>; }; + peri_c_subctrl: sub-ctrl-c@80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = < 0x0 0x80000000 0x0 0x10000>; + }; + uart0: uart@80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi index 606dd5a..da7b6e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi @@ -10,8 +10,8 @@ soc0: soc@000000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x803c0000 0x0 0x10000 - 0x0 0x80000000 0x0 0x10000>; + reg = <0x0 0x803c0000 0x0 0x10000>; + subctrl-vbase = <&peri_c_subctrl>; soc0_phy0: ethernet-phy@0 { reg = <0x0>; -- 1.9.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: yankejian@huawei.com (yankejian) Date: Mon, 7 Dec 2015 16:25:06 +0800 Subject: [PATCH v2 next 1/2] dts: hisi: fixes no syscon error when init mdio In-Reply-To: <1449476707-224320-1-git-send-email-yankejian@huawei.com> References: <1449476707-224320-1-git-send-email-yankejian@huawei.com> Message-ID: <1449476707-224320-2-git-send-email-yankejian@huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Signed-nux start up, we get the log below: "Hi-HNS_MDIO 803c0000.mdio: no syscon hisilicon,peri-c-subctrl mdio_bus mdio at 803c0000: mdio sys ctl reg has not maped " the source code about the subctrl is dealled with syscon, but dts doesn't. it cause such fault. so this patch adds the syscon info on dts files to fixes it. and it adds documentation for the devicetree bindings used by DT files of Hisilicon Hip05-D02 development board. Signed-off-by: yankejian --- change log: v2: 1) updates the related documented in the binding as well 2) use the normal naming conventions using '-' instead of '_' v1: initial version --- .../devicetree/bindings/arm/hisilicon/hisilicon.txt | 16 ++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 5 +++++ arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi | 4 ++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt index 6ac7c00..9f05767 100644 --- a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt +++ b/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt @@ -187,6 +187,22 @@ Example: reg = <0xb0000000 0x10000>; }; +Hisilicon HiP05 PERISUB system controller + +Required properties: +- compatible : "hisilicon,peri-c-subctrl", "syscon"; +- reg : Register address and size + +The HiP05 PERISUB system controller is shared by peripheral controllers in +HiP05 Soc to implement some basic configurations. the peripheral +controllers include mdio, ddr, iic, uart, timer and so on. + +Example: + /* for HiP05 PCIe-SAS system */ + peri-c-subctrl: sub-ctrl-c at 80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = <0x0 0x80000000 0x0 0x10000>; + }; ----------------------------------------------------------------------- Hisilicon CPU controller diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 4ff16d0..5fec740 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -246,6 +246,11 @@ clock-frequency = <200000000>; }; + peri_c_subctrl: sub-ctrl-c at 80000000 { + compatible = "hisilicon,peri-c-subctrl", "syscon"; + reg = < 0x0 0x80000000 0x0 0x10000>; + }; + uart0: uart at 80300000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x80300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi index 606dd5a..da7b6e6 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi @@ -10,8 +10,8 @@ soc0: soc at 000000000 { #address-cells = <1>; #size-cells = <0>; compatible = "hisilicon,hns-mdio"; - reg = <0x0 0x803c0000 0x0 0x10000 - 0x0 0x80000000 0x0 0x10000>; + reg = <0x0 0x803c0000 0x0 0x10000>; + subctrl-vbase = <&peri_c_subctrl>; soc0_phy0: ethernet-phy at 0 { reg = <0x0>; -- 1.9.1