* [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: devicetree, netdev, linux-kernel, linux-arm-kernel, Jisheng Zhang
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.
This series tries to addess the "more than one clk" issue. Note: to
support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
have mbus concept etc.
Since v2:
- Name the optional clock as "bus", which is a bit more flexible.
Since v1:
- Add Thomas Acks to patch1 and patch2.
- make sure the headers are really sorted (some headers are still
unsorted in v1).
- disable axi clk before disabling core clk, Thank Thomas.
- update dt binding as Thomas suggested.
Jisheng Zhang (4):
net: mvneta: sort the headers in alphabetic order
net: mvneta: Try to get named core clock first
net: mvneta: get optional bus clk
net: mvneta: update clocks property and document additional
clock-names
.../bindings/net/marvell-armada-370-neta.txt | 7 +++-
drivers/net/ethernet/marvell/mvneta.c | 38 ++++++++++++++--------
2 files changed, 30 insertions(+), 15 deletions(-)
--
2.7.0.rc3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.
This series tries to addess the "more than one clk" issue. Note: to
support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
have mbus concept etc.
Since v2:
- Name the optional clock as "bus", which is a bit more flexible.
Since v1:
- Add Thomas Acks to patch1 and patch2.
- make sure the headers are really sorted (some headers are still
unsorted in v1).
- disable axi clk before disabling core clk, Thank Thomas.
- update dt binding as Thomas suggested.
Jisheng Zhang (4):
net: mvneta: sort the headers in alphabetic order
net: mvneta: Try to get named core clock first
net: mvneta: get optional bus clk
net: mvneta: update clocks property and document additional
clock-names
.../bindings/net/marvell-armada-370-neta.txt | 7 +++-
drivers/net/ethernet/marvell/mvneta.c | 38 ++++++++++++++--------
2 files changed, 30 insertions(+), 15 deletions(-)
--
2.7.0.rc3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.
This series tries to addess the "more than one clk" issue. Note: to
support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
have mbus concept etc.
Since v2:
- Name the optional clock as "bus", which is a bit more flexible.
Since v1:
- Add Thomas Acks to patch1 and patch2.
- make sure the headers are really sorted (some headers are still
unsorted in v1).
- disable axi clk before disabling core clk, Thank Thomas.
- update dt binding as Thomas suggested.
Jisheng Zhang (4):
net: mvneta: sort the headers in alphabetic order
net: mvneta: Try to get named core clock first
net: mvneta: get optional bus clk
net: mvneta: update clocks property and document additional
clock-names
.../bindings/net/marvell-armada-370-neta.txt | 7 +++-
drivers/net/ethernet/marvell/mvneta.c | 38 ++++++++++++++--------
2 files changed, 30 insertions(+), 15 deletions(-)
--
2.7.0.rc3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: linux-arm-kernel
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides "core" clk for the mac core, and "axi"
clk for the AXI bus logic.
This series tries to addess the "more than one clk" issue. Note: to
support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
have mbus concept etc.
Since v2:
- Name the optional clock as "bus", which is a bit more flexible.
Since v1:
- Add Thomas Acks to patch1 and patch2.
- make sure the headers are really sorted (some headers are still
unsorted in v1).
- disable axi clk before disabling core clk, Thank Thomas.
- update dt binding as Thomas suggested.
Jisheng Zhang (4):
net: mvneta: sort the headers in alphabetic order
net: mvneta: Try to get named core clock first
net: mvneta: get optional bus clk
net: mvneta: update clocks property and document additional
clock-names
.../bindings/net/marvell-armada-370-neta.txt | 7 +++-
drivers/net/ethernet/marvell/mvneta.c | 38 ++++++++++++++--------
2 files changed, 30 insertions(+), 15 deletions(-)
--
2.7.0.rc3
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] net: mvneta: sort the headers in alphabetic order
2016-01-20 11:27 ` Jisheng Zhang
(?)
(?)
@ 2016-01-20 11:27 ` Jisheng Zhang
-1 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: devicetree, netdev, linux-kernel, linux-arm-kernel, Jisheng Zhang
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index fabc8df..8e85a53 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -11,28 +11,28 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/skbuff.h>
+#include <linux/if_vlan.h>
#include <linux/inetdevice.h>
-#include <linux/mbus.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
-#include <linux/if_vlan.h>
-#include <net/ip.h>
-#include <net/ipv6.h>
#include <linux/io.h>
-#include <net/tso.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/of_address.h>
#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/tso.h>
/* Registers */
#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] net: mvneta: sort the headers in alphabetic order
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index fabc8df..8e85a53 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -11,28 +11,28 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/skbuff.h>
+#include <linux/if_vlan.h>
#include <linux/inetdevice.h>
-#include <linux/mbus.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
-#include <linux/if_vlan.h>
-#include <net/ip.h>
-#include <net/ipv6.h>
#include <linux/io.h>
-#include <net/tso.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/of_address.h>
#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/tso.h>
/* Registers */
#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] net: mvneta: sort the headers in alphabetic order
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index fabc8df..8e85a53 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -11,28 +11,28 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/skbuff.h>
+#include <linux/if_vlan.h>
#include <linux/inetdevice.h>
-#include <linux/mbus.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
-#include <linux/if_vlan.h>
-#include <net/ip.h>
-#include <net/ipv6.h>
#include <linux/io.h>
-#include <net/tso.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/of_address.h>
#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/tso.h>
/* Registers */
#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 1/4] net: mvneta: sort the headers in alphabetic order
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: linux-arm-kernel
Sorting the headers in alphabetic order will help to reduce the conflict
when adding new headers in the future.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index fabc8df..8e85a53 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -11,28 +11,28 @@
* warranty of any kind, whether express or implied.
*/
-#include <linux/kernel.h>
-#include <linux/netdevice.h>
+#include <linux/clk.h>
+#include <linux/cpu.h>
#include <linux/etherdevice.h>
-#include <linux/platform_device.h>
-#include <linux/skbuff.h>
+#include <linux/if_vlan.h>
#include <linux/inetdevice.h>
-#include <linux/mbus.h>
-#include <linux/module.h>
#include <linux/interrupt.h>
-#include <linux/if_vlan.h>
-#include <net/ip.h>
-#include <net/ipv6.h>
#include <linux/io.h>
-#include <net/tso.h>
+#include <linux/kernel.h>
+#include <linux/mbus.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
-#include <linux/of_address.h>
#include <linux/phy.h>
-#include <linux/clk.h>
-#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/skbuff.h>
+#include <net/ip.h>
+#include <net/ipv6.h>
+#include <net/tso.h>
/* Registers */
#define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] net: mvneta: Try to get named core clock first
2016-01-20 11:27 ` Jisheng Zhang
(?)
(?)
@ 2016-01-20 11:27 ` Jisheng Zhang
-1 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: devicetree, netdev, linux-kernel, linux-arm-kernel, Jisheng Zhang
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic.
To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 8e85a53..736a9ec 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3605,7 +3605,9 @@ static int mvneta_probe(struct platform_device *pdev)
pp->indir[0] = rxq_def;
- pp->clk = devm_clk_get(&pdev->dev, NULL);
+ pp->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pp->clk))
+ pp->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pp->clk)) {
err = PTR_ERR(pp->clk);
goto err_put_phy_node;
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] net: mvneta: Try to get named core clock first
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic.
To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 8e85a53..736a9ec 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3605,7 +3605,9 @@ static int mvneta_probe(struct platform_device *pdev)
pp->indir[0] = rxq_def;
- pp->clk = devm_clk_get(&pdev->dev, NULL);
+ pp->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pp->clk))
+ pp->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pp->clk)) {
err = PTR_ERR(pp->clk);
goto err_put_phy_node;
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] net: mvneta: Try to get named core clock first
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic.
To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 8e85a53..736a9ec 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3605,7 +3605,9 @@ static int mvneta_probe(struct platform_device *pdev)
pp->indir[0] = rxq_def;
- pp->clk = devm_clk_get(&pdev->dev, NULL);
+ pp->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pp->clk))
+ pp->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pp->clk)) {
err = PTR_ERR(pp->clk);
goto err_put_phy_node;
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 2/4] net: mvneta: Try to get named core clock first
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: linux-arm-kernel
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic.
To support for more than one clock, we'll need to distinguish between
the clock by name. Change clock probing to first try to get "core"
clock before falling back to unnamed clock.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 8e85a53..736a9ec 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3605,7 +3605,9 @@ static int mvneta_probe(struct platform_device *pdev)
pp->indir[0] = rxq_def;
- pp->clk = devm_clk_get(&pdev->dev, NULL);
+ pp->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pp->clk))
+ pp->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pp->clk)) {
err = PTR_ERR(pp->clk);
goto err_put_phy_node;
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] net: mvneta: get optional bus clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: devicetree, netdev, linux-kernel, linux-arm-kernel, Jisheng Zhang
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic. Obviously this bus clk also need to
be enabled. This patch adds this optional "bus" clk support.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 736a9ec..8b306d2 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -373,6 +373,8 @@ struct mvneta_port {
/* Core clock */
struct clk *clk;
+ /* AXI clock */
+ struct clk *clk_bus;
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
clk_prepare_enable(pp->clk);
+ pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ if (!IS_ERR(pp->clk_bus))
+ clk_prepare_enable(pp->clk_bus);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pp->base)) {
@@ -3726,6 +3732,7 @@ err_free_stats:
err_free_ports:
free_percpu(pp->ports);
err_clk:
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
err_put_phy_node:
of_node_put(phy_node);
@@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev)
struct mvneta_port *pp = netdev_priv(dev);
unregister_netdev(dev);
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
free_percpu(pp->ports);
free_percpu(pp->stats);
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] net: mvneta: get optional bus clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, mw-nYOzD4b6Jr9Wk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jisheng Zhang
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic. Obviously this bus clk also need to
be enabled. This patch adds this optional "bus" clk support.
Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
---
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 736a9ec..8b306d2 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -373,6 +373,8 @@ struct mvneta_port {
/* Core clock */
struct clk *clk;
+ /* AXI clock */
+ struct clk *clk_bus;
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
clk_prepare_enable(pp->clk);
+ pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ if (!IS_ERR(pp->clk_bus))
+ clk_prepare_enable(pp->clk_bus);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pp->base)) {
@@ -3726,6 +3732,7 @@ err_free_stats:
err_free_ports:
free_percpu(pp->ports);
err_clk:
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
err_put_phy_node:
of_node_put(phy_node);
@@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev)
struct mvneta_port *pp = netdev_priv(dev);
unregister_netdev(dev);
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
free_percpu(pp->ports);
free_percpu(pp->stats);
--
2.7.0.rc3
--
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] net: mvneta: get optional bus clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, mw-nYOzD4b6Jr9Wk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jisheng Zhang
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic. Obviously this bus clk also need to
be enabled. This patch adds this optional "bus" clk support.
Signed-off-by: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
---
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 736a9ec..8b306d2 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -373,6 +373,8 @@ struct mvneta_port {
/* Core clock */
struct clk *clk;
+ /* AXI clock */
+ struct clk *clk_bus;
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
clk_prepare_enable(pp->clk);
+ pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ if (!IS_ERR(pp->clk_bus))
+ clk_prepare_enable(pp->clk_bus);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pp->base)) {
@@ -3726,6 +3732,7 @@ err_free_stats:
err_free_ports:
free_percpu(pp->ports);
err_clk:
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
err_put_phy_node:
of_node_put(phy_node);
@@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev)
struct mvneta_port *pp = netdev_priv(dev);
unregister_netdev(dev);
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
free_percpu(pp->ports);
free_percpu(pp->stats);
--
2.7.0.rc3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 3/4] net: mvneta: get optional bus clk
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: linux-arm-kernel
Some platforms may provide more than one clk for the mvneta IP, for
example Marvell BG4CT provides one clk for the mac core, and one
clk for the AXI bus logic. Obviously this bus clk also need to
be enabled. This patch adds this optional "bus" clk support.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 736a9ec..8b306d2 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -373,6 +373,8 @@ struct mvneta_port {
/* Core clock */
struct clk *clk;
+ /* AXI clock */
+ struct clk *clk_bus;
u8 mcast_count[256];
u16 tx_ring_size;
u16 rx_ring_size;
@@ -3615,6 +3617,10 @@ static int mvneta_probe(struct platform_device *pdev)
clk_prepare_enable(pp->clk);
+ pp->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ if (!IS_ERR(pp->clk_bus))
+ clk_prepare_enable(pp->clk_bus);
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pp->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(pp->base)) {
@@ -3726,6 +3732,7 @@ err_free_stats:
err_free_ports:
free_percpu(pp->ports);
err_clk:
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
err_put_phy_node:
of_node_put(phy_node);
@@ -3743,6 +3750,7 @@ static int mvneta_remove(struct platform_device *pdev)
struct mvneta_port *pp = netdev_priv(dev);
unregister_netdev(dev);
+ clk_disable_unprepare(pp->clk_bus);
clk_disable_unprepare(pp->clk);
free_percpu(pp->ports);
free_percpu(pp->stats);
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
2016-01-20 11:27 ` Jisheng Zhang
(?)
(?)
@ 2016-01-20 11:27 ` Jisheng Zhang
-1 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: devicetree, netdev, linux-kernel, linux-arm-kernel, Jisheng Zhang
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index aeea50c..d0cb869 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -6,12 +6,17 @@ Required properties:
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory
-- clocks: a pointer to the reference clock for this device.
+- clocks: List of clocks for this device. At least one clock is
+ mandatory for the core clock. If several clocks are given, then the
+ clock-names property must be used to identify them.
Optional properties:
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
Value is presented in bytes. If not used, by default 1600B is set for
"marvell,armada-370-neta" and 9800B for others.
+- clock-names: List of names corresponding to clocks property; shall be
+ "core" for core clock and "bus" for the optional bus clock.
+
Example:
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index aeea50c..d0cb869 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -6,12 +6,17 @@ Required properties:
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory
-- clocks: a pointer to the reference clock for this device.
+- clocks: List of clocks for this device. At least one clock is
+ mandatory for the core clock. If several clocks are given, then the
+ clock-names property must be used to identify them.
Optional properties:
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
Value is presented in bytes. If not used, by default 1600B is set for
"marvell,armada-370-neta" and 9800B for others.
+- clock-names: List of names corresponding to clocks property; shall be
+ "core" for core clock and "bus" for the optional bus clock.
+
Example:
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: thomas.petazzoni, davem, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth
Cc: Jisheng Zhang, devicetree, linux-kernel, linux-arm-kernel, netdev
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index aeea50c..d0cb869 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -6,12 +6,17 @@ Required properties:
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory
-- clocks: a pointer to the reference clock for this device.
+- clocks: List of clocks for this device. At least one clock is
+ mandatory for the core clock. If several clocks are given, then the
+ clock-names property must be used to identify them.
Optional properties:
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
Value is presented in bytes. If not used, by default 1600B is set for
"marvell,armada-370-neta" and 9800B for others.
+- clock-names: List of names corresponding to clocks property; shall be
+ "core" for core clock and "bus" for the optional bus clock.
+
Example:
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
@ 2016-01-20 11:27 ` Jisheng Zhang
0 siblings, 0 replies; 25+ messages in thread
From: Jisheng Zhang @ 2016-01-20 11:27 UTC (permalink / raw
To: linux-arm-kernel
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index aeea50c..d0cb869 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -6,12 +6,17 @@ Required properties:
- interrupts: interrupt for the device
- phy: See ethernet.txt file in the same directory.
- phy-mode: See ethernet.txt file in the same directory
-- clocks: a pointer to the reference clock for this device.
+- clocks: List of clocks for this device. At least one clock is
+ mandatory for the core clock. If several clocks are given, then the
+ clock-names property must be used to identify them.
Optional properties:
- tx-csum-limit: maximum mtu supported by port that allow TX checksum.
Value is presented in bytes. If not used, by default 1600B is set for
"marvell,armada-370-neta" and 9800B for others.
+- clock-names: List of names corresponding to clocks property; shall be
+ "core" for core clock and "bus" for the optional bus clock.
+
Example:
--
2.7.0.rc3
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
2016-01-20 11:27 ` Jisheng Zhang
@ 2016-01-20 16:29 ` Rob Herring
-1 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2016-01-20 16:29 UTC (permalink / raw
To: Jisheng Zhang
Cc: thomas.petazzoni, davem, mw, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth, devicetree, netdev,
linux-kernel, linux-arm-kernel
On Wed, Jan 20, 2016 at 07:27:25PM +0800, Jisheng Zhang wrote:
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names
@ 2016-01-20 16:29 ` Rob Herring
0 siblings, 0 replies; 25+ messages in thread
From: Rob Herring @ 2016-01-20 16:29 UTC (permalink / raw
To: linux-arm-kernel
On Wed, Jan 20, 2016 at 07:27:25PM +0800, Jisheng Zhang wrote:
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> ---
> Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-21 20:05 ` David Miller
0 siblings, 0 replies; 25+ messages in thread
From: David Miller @ 2016-01-21 20:05 UTC (permalink / raw
To: jszhang
Cc: thomas.petazzoni, mw, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, sebastian.hesselbarth, devicetree, netdev,
linux-kernel, linux-arm-kernel
From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 20 Jan 2016 19:27:21 +0800
> Some platforms may provide more than one clk for the mvneta IP, for
> example Marvell BG4CT provides "core" clk for the mac core, and "axi"
> clk for the AXI bus logic.
>
> This series tries to addess the "more than one clk" issue. Note: to
> support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
> have mbus concept etc.
>
> Since v2:
> - Name the optional clock as "bus", which is a bit more flexible.
>
> Since v1:
> - Add Thomas Acks to patch1 and patch2.
> - make sure the headers are really sorted (some headers are still
> unsorted in v1).
> - disable axi clk before disabling core clk, Thank Thomas.
> - update dt binding as Thomas suggested.
Series applied, thanks.
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-21 20:05 ` David Miller
0 siblings, 0 replies; 25+ messages in thread
From: David Miller @ 2016-01-21 20:05 UTC (permalink / raw
To: jszhang-eYqpPyKDWXRBDgjK7y7TUQ
Cc: thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
mw-nYOzD4b6Jr9Wk0Htik3J/w, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA, netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
From: Jisheng Zhang <jszhang-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Date: Wed, 20 Jan 2016 19:27:21 +0800
> Some platforms may provide more than one clk for the mvneta IP, for
> example Marvell BG4CT provides "core" clk for the mac core, and "axi"
> clk for the AXI bus logic.
>
> This series tries to addess the "more than one clk" issue. Note: to
> support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
> have mbus concept etc.
>
> Since v2:
> - Name the optional clock as "bus", which is a bit more flexible.
>
> Since v1:
> - Add Thomas Acks to patch1 and patch2.
> - make sure the headers are really sorted (some headers are still
> unsorted in v1).
> - disable axi clk before disabling core clk, Thank Thomas.
> - update dt binding as Thomas suggested.
Series applied, thanks.
--
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v3 0/4] net: mvneta: support more than one clk
@ 2016-01-21 20:05 ` David Miller
0 siblings, 0 replies; 25+ messages in thread
From: David Miller @ 2016-01-21 20:05 UTC (permalink / raw
To: linux-arm-kernel
From: Jisheng Zhang <jszhang@marvell.com>
Date: Wed, 20 Jan 2016 19:27:21 +0800
> Some platforms may provide more than one clk for the mvneta IP, for
> example Marvell BG4CT provides "core" clk for the mac core, and "axi"
> clk for the AXI bus logic.
>
> This series tries to addess the "more than one clk" issue. Note: to
> support BG4CT, we have lots of refactor work to do, eg. BG4CT doesn't
> have mbus concept etc.
>
> Since v2:
> - Name the optional clock as "bus", which is a bit more flexible.
>
> Since v1:
> - Add Thomas Acks to patch1 and patch2.
> - make sure the headers are really sorted (some headers are still
> unsorted in v1).
> - disable axi clk before disabling core clk, Thank Thomas.
> - update dt binding as Thomas suggested.
Series applied, thanks.
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2016-01-21 20:05 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-01-20 11:27 [PATCH v3 0/4] net: mvneta: support more than one clk Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` [PATCH v3 1/4] net: mvneta: sort the headers in alphabetic order Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` [PATCH v3 2/4] net: mvneta: Try to get named core clock first Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` [PATCH v3 3/4] net: mvneta: get optional bus clk Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` [PATCH v3 4/4] net: mvneta: update clocks property and document additional clock-names Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 11:27 ` Jisheng Zhang
2016-01-20 16:29 ` Rob Herring
2016-01-20 16:29 ` Rob Herring
2016-01-21 20:05 ` [PATCH v3 0/4] net: mvneta: support more than one clk David Miller
2016-01-21 20:05 ` David Miller
2016-01-21 20:05 ` David Miller
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