* [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso
@ 2019-08-14 20:40 Andrey Grodzovsky
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
This patchset adds mode 2 reset through SMU for RV2 and Picasso.
v2:
Split into more patches per functional unit.
Add some NULL checks and fix typos.
Andrey Grodzovsky (5):
drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG
drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr
drm/amd/powerpay: Implement mode2 reset callback for SMU10
drm/amd/poweplay: Add amd_pm_funcs callback for mode 2
drm/amdgpu: Use new mode2 reset interface for RV.
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++++++++++++++--------
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 21 +++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 ++++++++
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
7 files changed, 57 insertions(+), 9 deletions(-)
--
2.7.4
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v2 1/5] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-14 20:40 ` Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 2/5] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr Andrey Grodzovsky
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
By comparing to windows it means ASIC reset.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
index 90879e4..df4677d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h
@@ -59,7 +59,7 @@
#define PPSMC_MSG_SetDriverDramAddrLow 0x1B
#define PPSMC_MSG_TransferTableSmu2Dram 0x1C
#define PPSMC_MSG_TransferTableDram2Smu 0x1D
-#define PPSMC_MSG_ControlGfxRM 0x1E
+#define PPSMC_MSG_DeviceDriverReset 0x1E
#define PPSMC_MSG_SetGfxclkOverdriveByFreqVid 0x1F
#define PPSMC_MSG_SetHardMinDcefclkByFreq 0x20
#define PPSMC_MSG_SetHardMinSocclkByFreq 0x21
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/5] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-08-14 20:40 ` [PATCH v2 1/5] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG Andrey Grodzovsky
@ 2019-08-14 20:40 ` Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 3/5] drm/amd/powerpay: Implement mode2 reset callback for SMU10 Andrey Grodzovsky
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
Also define reset modes (0, 1 and 2)
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index 07fd64a..abeff15 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -189,6 +189,14 @@ struct phm_vce_clock_voltage_dependency_table {
struct phm_vce_clock_voltage_dependency_record entries[1];
};
+
+enum SMU_ASIC_RESET_MODE
+{
+ SMU_ASIC_RESET_MODE_0,
+ SMU_ASIC_RESET_MODE_1,
+ SMU_ASIC_RESET_MODE_2,
+};
+
struct pp_smumgr_func {
char *name;
int (*smu_init)(struct pp_hwmgr *hwmgr);
@@ -345,6 +353,7 @@ struct pp_hwmgr_func {
int (*get_ppfeature_status)(struct pp_hwmgr *hwmgr, char *buf);
int (*set_ppfeature_status)(struct pp_hwmgr *hwmgr, uint64_t ppfeature_masks);
int (*set_mp1_state)(struct pp_hwmgr *hwmgr, enum pp_mp1_state mp1_state);
+ int (*asic_reset)(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode);
};
struct pp_table_func {
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/5] drm/amd/powerpay: Implement mode2 reset callback for SMU10
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-08-14 20:40 ` [PATCH v2 1/5] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 2/5] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr Andrey Grodzovsky
@ 2019-08-14 20:40 ` Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 4/5] drm/amd/poweplay: Add amd_pm_funcs callback for mode 2 Andrey Grodzovsky
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index 18e780f..1115761 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -1311,6 +1311,12 @@ static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uin
return 0;
}
+static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
+{
+ return smum_send_msg_to_smc_with_parameter(hwmgr,
+ PPSMC_MSG_DeviceDriverReset,
+ mode);
+}
static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
.backend_init = smu10_hwmgr_backend_init,
@@ -1355,6 +1361,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
.get_power_profile_mode = smu10_get_power_profile_mode,
.set_power_profile_mode = smu10_set_power_profile_mode,
+ .asic_reset = smu10_asic_reset,
};
int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/5] drm/amd/poweplay: Add amd_pm_funcs callback for mode 2
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2019-08-14 20:40 ` [PATCH v2 3/5] drm/amd/powerpay: Implement mode2 reset callback for SMU10 Andrey Grodzovsky
@ 2019-08-14 20:40 ` Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV Andrey Grodzovsky
2019-08-14 20:51 ` [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso Deucher, Alexander
5 siblings, 0 replies; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 21 +++++++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index bba1291..0de4e37 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -310,6 +310,7 @@ struct amd_pm_funcs {
int (*set_asic_baco_state)(void *handle, int state);
int (*get_ppfeature_status)(void *handle, char *buf);
int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
+ int (*asic_reset_mode_2)(void *handle);
};
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 2e3d9ef6..7ef2027 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -1508,6 +1508,26 @@ static int pp_set_ppfeature_status(void *handle, uint64_t ppfeature_masks)
return ret;
}
+static int pp_asic_reset_mode_2(void *handle)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
+
+ if (!hwmgr || !hwmgr->pm_en)
+ return -EINVAL;
+
+ if (hwmgr->hwmgr_func->asic_reset == NULL) {
+ pr_info_ratelimited("%s was not implemented.\n", __func__);
+ return -EINVAL;
+ }
+
+ mutex_lock(&hwmgr->smu_lock);
+ ret = hwmgr->hwmgr_func->asic_reset(hwmgr, SMU_ASIC_RESET_MODE_2);
+ mutex_unlock(&hwmgr->smu_lock);
+
+ return ret;
+}
+
static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
@@ -1564,4 +1584,5 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
.set_asic_baco_state = pp_set_asic_baco_state,
.get_ppfeature_status = pp_get_ppfeature_status,
.set_ppfeature_status = pp_set_ppfeature_status,
+ .asic_reset_mode_2 = pp_asic_reset_mode_2,
};
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV.
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
` (3 preceding siblings ...)
2019-08-14 20:40 ` [PATCH v2 4/5] drm/amd/poweplay: Add amd_pm_funcs callback for mode 2 Andrey Grodzovsky
@ 2019-08-14 20:40 ` Andrey Grodzovsky
[not found] ` <1565815217-9533-6-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-08-14 20:51 ` [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso Deucher, Alexander
5 siblings, 1 reply; 8+ messages in thread
From: Andrey Grodzovsky @ 2019-08-14 20:40 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
evan.quan-5C7GfCeVMHo, Shirish.S-5C7GfCeVMHo
v2:
Check ppfuncs pointer for NULL
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++++++++++++++++--------
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2752773..02b3e7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3524,6 +3524,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
case CHIP_VEGA20:
case CHIP_VEGA10:
case CHIP_VEGA12:
+ case CHIP_RAVEN:
break;
default:
goto disabled;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c2d324d..77e6799 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -508,6 +508,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
return 0;
}
+static int soc15_mode2_reset(struct amdgpu_device *adev)
+{
+ if (!adev->powerplay.pp_funcs ||
+ !adev->powerplay.pp_funcs->asic_reset_mode_2)
+ return -ENOENT;
+
+ return adev->powerplay.pp_funcs->asic_reset_mode_2(adev->powerplay.pp_handle);
+}
+
static enum amd_reset_method
soc15_asic_reset_method(struct amdgpu_device *adev)
{
@@ -546,14 +555,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
static int soc15_asic_reset(struct amdgpu_device *adev)
{
- int ret;
-
- if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
- ret = soc15_asic_baco_reset(adev);
- else
- ret = soc15_asic_mode1_reset(adev);
-
- return ret;
+ switch (soc15_asic_reset_method(adev)) {
+ case AMD_RESET_METHOD_BACO:
+ return soc15_asic_baco_reset(adev);
+ case AMD_RESET_METHOD_MODE2:
+ return soc15_mode2_reset(adev);
+ default:
+ return soc15_asic_mode1_reset(adev);
+ }
}
/*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
--
2.7.4
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^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
` (4 preceding siblings ...)
2019-08-14 20:40 ` [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV Andrey Grodzovsky
@ 2019-08-14 20:51 ` Deucher, Alexander
5 siblings, 0 replies; 8+ messages in thread
From: Deucher, Alexander @ 2019-08-14 20:51 UTC (permalink / raw
To: Grodzovsky, Andrey,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Quan, Evan, S, Shirish
[-- Attachment #1.1: Type: text/plain, Size: 2022 bytes --]
Please add patch descriptions for patches 3, 4, 5. With that fixed, series is:
Reviewed-by: Alex Deucher <alexander.deucher-5C7GfCeVMHo@public.gmane.org>
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Andrey Grodzovsky <andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, August 14, 2019 4:40 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org <amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Grodzovsky, Andrey <Andrey.Grodzovsky-5C7GfCeVMHo@public.gmane.org>; Quan, Evan <Evan.Quan-5C7GfCeVMHo@public.gmane.org>; S, Shirish <Shirish.S-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso
This patchset adds mode 2 reset through SMU for RV2 and Picasso.
v2:
Split into more patches per functional unit.
Add some NULL checks and fix typos.
Andrey Grodzovsky (5):
drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG
drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr
drm/amd/powerpay: Implement mode2 reset callback for SMU10
drm/amd/poweplay: Add amd_pm_funcs callback for mode 2
drm/amdgpu: Use new mode2 reset interface for RV.
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++++++++++++++--------
drivers/gpu/drm/amd/include/kgd_pp_interface.h | 1 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 21 +++++++++++++++++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 7 +++++++
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 9 ++++++++
drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h | 2 +-
7 files changed, 57 insertions(+), 9 deletions(-)
--
2.7.4
_______________________________________________
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amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[-- Attachment #1.2: Type: text/html, Size: 3590 bytes --]
[-- Attachment #2: Type: text/plain, Size: 153 bytes --]
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV.
[not found] ` <1565815217-9533-6-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
@ 2019-08-15 1:29 ` Quan, Evan
0 siblings, 0 replies; 8+ messages in thread
From: Quan, Evan @ 2019-08-15 1:29 UTC (permalink / raw
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander, Grodzovsky, Andrey, S, Shirish
Series is Reviewed-by: Evan Quan <evan.quan@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Andrey Grodzovsky
> Sent: Thursday, August 15, 2019 4:40 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky,
> Andrey <Andrey.Grodzovsky@amd.com>; Quan, Evan
> <Evan.Quan@amd.com>; S, Shirish <Shirish.S@amd.com>
> Subject: [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV.
>
> v2:
> Check ppfuncs pointer for NULL
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
> drivers/gpu/drm/amd/amdgpu/soc15.c | 25 +++++++++++++++++-------
> -
> 2 files changed, 18 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2752773..02b3e7d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3524,6 +3524,7 @@ bool amdgpu_device_should_recover_gpu(struct
> amdgpu_device *adev)
> case CHIP_VEGA20:
> case CHIP_VEGA10:
> case CHIP_VEGA12:
> + case CHIP_RAVEN:
> break;
> default:
> goto disabled;
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index c2d324d..77e6799 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -508,6 +508,15 @@ static int soc15_asic_baco_reset(struct
> amdgpu_device *adev)
> return 0;
> }
>
> +static int soc15_mode2_reset(struct amdgpu_device *adev) {
> + if (!adev->powerplay.pp_funcs ||
> + !adev->powerplay.pp_funcs->asic_reset_mode_2)
> + return -ENOENT;
> +
> + return
> +adev->powerplay.pp_funcs->asic_reset_mode_2(adev-
> >powerplay.pp_handle);
> +}
> +
> static enum amd_reset_method
> soc15_asic_reset_method(struct amdgpu_device *adev) { @@ -546,14
> +555,14 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
>
> static int soc15_asic_reset(struct amdgpu_device *adev) {
> - int ret;
> -
> - if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
> - ret = soc15_asic_baco_reset(adev);
> - else
> - ret = soc15_asic_mode1_reset(adev);
> -
> - return ret;
> + switch (soc15_asic_reset_method(adev)) {
> + case AMD_RESET_METHOD_BACO:
> + return soc15_asic_baco_reset(adev);
> + case AMD_RESET_METHOD_MODE2:
> + return soc15_mode2_reset(adev);
> + default:
> + return soc15_asic_mode1_reset(adev);
> + }
> }
>
> /*static int soc15_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2019-08-15 1:29 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-08-14 20:40 [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso Andrey Grodzovsky
[not found] ` <1565815217-9533-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-08-14 20:40 ` [PATCH v2 1/5] drm/amd/powerplay: Fix meaning of 0x1E PPSMC_MSG Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 2/5] drm/amd/powerplay: add mode2 reset callback for pp_smu_mgr Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 3/5] drm/amd/powerpay: Implement mode2 reset callback for SMU10 Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 4/5] drm/amd/poweplay: Add amd_pm_funcs callback for mode 2 Andrey Grodzovsky
2019-08-14 20:40 ` [PATCH v2 5/5] drm/amdgpu: Use new mode2 reset interface for RV Andrey Grodzovsky
[not found] ` <1565815217-9533-6-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2019-08-15 1:29 ` Quan, Evan
2019-08-14 20:51 ` [PATCH v2 0/5] Add mode 2 GPU reset for RV2/Picasso Deucher, Alexander
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