* Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2.
@ 2019-11-23 2:32 Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-23 2:32 UTC (permalink / raw
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, paulburton,
jhogan, mripard, shawnguo, mark.rutland, syq, ralf, heiko,
icenowy, laurent.pinchart, krzk, geert+renesas, paul,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
v1->v2:
Rebase on top of mips-next, use ingenic-timer driver
for system timer and clocksource.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support.
2019-11-23 2:32 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2 Zhou Yanjie
@ 2019-11-23 2:32 ` Zhou Yanjie
2019-11-24 13:09 ` Paul Cercueil
2019-11-23 2:32 ` [PATCH v2 2/4] dt-bindings: Document yna vendor-prefix Zhou Yanjie
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-23 2:32 UTC (permalink / raw
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, paulburton,
jhogan, mripard, shawnguo, mark.rutland, syq, ralf, heiko,
icenowy, laurent.pinchart, krzk, geert+renesas, paul,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
Support the Ingenic X1000 SoC using the code under arch/mips/jz4740.
This is left unselectable in Kconfig until a X1000 based board is
added in a later commit.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Notes:
v1->v2:
Rebase on top of mips-next, use ingenic-timer driver
for system timer and clocksource.
arch/mips/boot/dts/ingenic/x1000.dtsi | 183 ++++++++++++++++++++++++++++++++++
arch/mips/jz4740/Kconfig | 6 ++
2 files changed, 189 insertions(+)
create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
new file mode 100644
index 00000000..02a9b2a
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/clock/x1000-cgu.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ingenic,x1000", "ingenic,x1000e";
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ intc: interrupt-controller@10001000 {
+ compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
+ reg = <0x10001000 0x50>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+
+ exclk: ext {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ };
+
+ rtclk: rtc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ cgu: x1000-cgu@10000000 {
+ compatible = "ingenic,x1000-cgu";
+ reg = <0x10000000 0x100>;
+
+ #clock-cells = <1>;
+
+ clocks = <&exclk>, <&rtclk>;
+ clock-names = "ext", "rtc";
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <>;
+
+ tcu: timer@10002000 {
+ compatible = "ingenic,x1000-tcu",
+ "ingenic,jz4770-tcu",
+ "simple-mfd";
+ reg = <0x10002000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x10002000 0x1000>;
+
+ #clock-cells = <1>;
+
+ clocks = <&cgu X1000_CLK_RTCLK
+ &cgu X1000_CLK_EXCLK
+ &cgu X1000_CLK_PCLK>;
+ clock-names = "rtc", "ext", "pclk";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <27 26 25>;
+ };
+
+ uart0: serial@10030000 {
+ compatible = "ingenic,x1000-uart";
+ reg = <0x10030000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <51>;
+
+ clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ uart1: serial@10031000 {
+ compatible = "ingenic,x1000-uart";
+ reg = <0x10031000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <50>;
+
+ clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ uart2: serial@10032000 {
+ compatible = "ingenic,x1000-uart";
+ reg = <0x10032000 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <49>;
+
+ clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
+ clock-names = "baud", "module";
+
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller@10010000 {
+ compatible = "ingenic,x1000-pinctrl";
+ reg = <0x10010000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpa: gpio@0 {
+ compatible = "ingenic,x1000-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+
+ gpb: gpio@1 {
+ compatible = "ingenic,x1000-gpio";
+ reg = <1>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ };
+
+ gpc: gpio@2 {
+ compatible = "ingenic,x1000-gpio";
+ reg = <2>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <15>;
+ };
+
+ gpd: gpio@3 {
+ compatible = "ingenic,x1000-gpio";
+ reg = <3>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <14>;
+ };
+ };
+ };
+};
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 4dd0c44..6b96844 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -33,3 +33,9 @@ config MACH_JZ4780
select MIPS_CPU_SCACHE
select SYS_HAS_CPU_MIPS32_R2
select SYS_SUPPORTS_HIGHMEM
+
+config MACH_X1000
+ bool
+ select MIPS_CPU_SCACHE
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_SUPPORTS_HIGHMEM
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/4] dt-bindings: Document yna vendor-prefix.
2019-11-23 2:32 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2 Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
@ 2019-11-23 2:32 ` Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 3/4] dt-bindings: MIPS: Add Ingenic XBurst based boards Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 4/4] MIPS: Ingenic: Initial YSH & ATIL CU Neo board. support Zhou Yanjie
3 siblings, 0 replies; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-23 2:32 UTC (permalink / raw
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, paulburton,
jhogan, mripard, shawnguo, mark.rutland, syq, ralf, heiko,
icenowy, laurent.pinchart, krzk, geert+renesas, paul,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
The "yna" is an acronym of the "YSH & ATIL".
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Notes:
v1->v2:
No change.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 967e78c..47ddd88 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1054,6 +1054,8 @@ patternProperties:
description: Xilinx
"^xunlong,.*":
description: Shenzhen Xunlong Software CO.,Limited
+ "^yna,.*":
+ description: YSH & ATIL
"^yones-toptech,.*":
description: Yones Toptech Co., Ltd.
"^ysoft,.*":
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] dt-bindings: MIPS: Add Ingenic XBurst based boards.
2019-11-23 2:32 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2 Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 2/4] dt-bindings: Document yna vendor-prefix Zhou Yanjie
@ 2019-11-23 2:32 ` Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 4/4] MIPS: Ingenic: Initial YSH & ATIL CU Neo board. support Zhou Yanjie
3 siblings, 0 replies; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-23 2:32 UTC (permalink / raw
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, paulburton,
jhogan, mripard, shawnguo, mark.rutland, syq, ralf, heiko,
icenowy, laurent.pinchart, krzk, geert+renesas, paul,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
Add Ingenic XBurst based boards, prepare for later dts.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Notes:
v1->v2:
No change.
.../devicetree/bindings/mips/ingenic/devices.yaml | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/devices.yaml
diff --git a/Documentation/devicetree/bindings/mips/ingenic/devices.yaml b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml
new file mode 100644
index 00000000..8bb4b5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/devices.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/ingenic/devices.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic XBurst based Platforms Device Tree Bindings
+
+maintainers:
+ - Zhou Yanjie <zhouyanjie@zoho.com>
+description: |
+ Devices with a Ingenic XBurst CPU shall have the following properties.
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+
+ - description: Qi Hardware Ben NanoNote
+ items:
+ - const: qi,lb60
+
+ - description: Game Consoles Worldwide GCW Zero
+ items:
+ - const: gcw,zero
+
+ - description: MIPS Creator CI20
+ items:
+ - const: img,ci20
+
+ - description: YSH & ATIL General Module CU Neo
+ items:
+ - const: yna,cu1000
+...
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 4/4] MIPS: Ingenic: Initial YSH & ATIL CU Neo board. support.
2019-11-23 2:32 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2 Zhou Yanjie
` (2 preceding siblings ...)
2019-11-23 2:32 ` [PATCH v2 3/4] dt-bindings: MIPS: Add Ingenic XBurst based boards Zhou Yanjie
@ 2019-11-23 2:32 ` Zhou Yanjie
3 siblings, 0 replies; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-23 2:32 UTC (permalink / raw
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, paulburton,
jhogan, mripard, shawnguo, mark.rutland, syq, ralf, heiko,
icenowy, laurent.pinchart, krzk, geert+renesas, paul,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
Add a device tree for the Ingenic X1000 based YSH & ATIL CU Neo board.
Note that this is unselectable via Kconfig until the X1000 SoC is made
selectable in a later commit.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Notes:
v1->v2:
Rebase on top of mips-next, use TCU for system timer and clocksource.
arch/mips/boot/dts/ingenic/Makefile | 1 +
arch/mips/boot/dts/ingenic/cu1000.dts | 52 ++++++++++++++++++
arch/mips/configs/cu1000_defconfig | 100 ++++++++++++++++++++++++++++++++++
arch/mips/jz4740/Kconfig | 4 ++
4 files changed, 157 insertions(+)
create mode 100644 arch/mips/boot/dts/ingenic/cu1000.dts
create mode 100644 arch/mips/configs/cu1000_defconfig
diff --git a/arch/mips/boot/dts/ingenic/Makefile b/arch/mips/boot/dts/ingenic/Makefile
index 9cc4844..f6db7bb 100644
--- a/arch/mips/boot/dts/ingenic/Makefile
+++ b/arch/mips/boot/dts/ingenic/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_JZ4740_QI_LB60) += qi_lb60.dtb
dtb-$(CONFIG_JZ4770_GCW0) += gcw0.dtb
dtb-$(CONFIG_JZ4780_CI20) += ci20.dtb
+dtb-$(CONFIG_X1000_CU1000) += cu1000.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/ingenic/cu1000.dts b/arch/mips/boot/dts/ingenic/cu1000.dts
new file mode 100644
index 00000000..b19872d
--- /dev/null
+++ b/arch/mips/boot/dts/ingenic/cu1000.dts
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include "x1000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/ingenic,tcu.h>
+
+/ {
+ compatible = "yna,cu1000", "ingenic,x1000";
+ model = "YSH & ATIL General Module CU Neo";
+
+ aliases {
+ serial2 = &uart2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x04000000>;
+ };
+};
+
+&exclk {
+ clock-frequency = <24000000>;
+};
+
+&tcu {
+ /* 1500 kHz for the system timer and clocksource */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER2>;
+ assigned-clock-rates = <1500000>, <1500000>;
+
+ /* Use channel #1 for the system timer channel #2 for the clocksource */
+ ingenic,pwm-channels-mask = <0xfa>;
+};
+
+&uart2 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_uart2>;
+};
+
+&pinctrl {
+ pins_uart2: uart2 {
+ function = "uart2";
+ groups = "uart2-data-d";
+ bias-disable;
+ };
+};
diff --git a/arch/mips/configs/cu1000_defconfig b/arch/mips/configs/cu1000_defconfig
new file mode 100644
index 00000000..88729ee
--- /dev/null
+++ b/arch/mips/configs/cu1000_defconfig
@@ -0,0 +1,100 @@
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_KERNEL_GZIP=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_KMEM=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="arch/mips/boot/ramdisk.cpio.gz"
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MACH_INGENIC=y
+CONFIG_X1000_CU1000=y
+CONFIG_HIGHMEM=y
+CONFIG_HZ_100=y
+CONFIG_HZ=100
+# CONFIG_SECCOMP is not set
+# CONFIG_SUSPEND is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_COMPACTION is not set
+CONFIG_CMA=y
+CONFIG_CMA_AREAS=7
+CONFIG_UEVENT_HELPER=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=2
+CONFIG_SERIAL_EARLYCON=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=3
+CONFIG_SERIAL_8250_RUNTIME_UARTS=3
+CONFIG_SERIAL_8250_INGENIC=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_EXT4_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_PROC_KCORE=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_AES=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_PRINTK_TIME=y
+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
+CONFIG_CONSOLE_LOGLEVEL_QUIET=15
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_DEBUG_INFO=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_STACKTRACE=y
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS2,115200n8 mem=32M@0x0 earlycon clk_ignore_unused"
+CONFIG_CMDLINE_OVERRIDE=y
diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
index 6b96844..b4cee0a 100644
--- a/arch/mips/jz4740/Kconfig
+++ b/arch/mips/jz4740/Kconfig
@@ -16,6 +16,10 @@ config JZ4780_CI20
bool "MIPS Creator CI20"
select MACH_JZ4780
+config X1000_CU1000
+ bool "YSH & ATIL General Module CU Neo"
+ select MACH_X1000
+
endchoice
config MACH_JZ4740
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support.
2019-11-23 2:32 ` [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
@ 2019-11-24 13:09 ` Paul Cercueil
2019-11-24 14:41 ` Zhou Yanjie
0 siblings, 1 reply; 7+ messages in thread
From: Paul Cercueil @ 2019-11-24 13:09 UTC (permalink / raw
To: Zhou Yanjie
Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
paulburton, jhogan, mripard, shawnguo, mark.rutland, syq, ralf,
heiko, icenowy, laurent.pinchart, krzk, geert+renesas,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
Hi Zhou,
Le sam., nov. 23, 2019 at 10:32, Zhou Yanjie <zhouyanjie@zoho.com> a
écrit :
> Support the Ingenic X1000 SoC using the code under arch/mips/jz4740.
> This is left unselectable in Kconfig until a X1000 based board is
> added in a later commit.
>
> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
> ---
>
> Notes:
> v1->v2:
> Rebase on top of mips-next, use ingenic-timer driver
> for system timer and clocksource.
>
> arch/mips/boot/dts/ingenic/x1000.dtsi | 183
> ++++++++++++++++++++++++++++++++++
> arch/mips/jz4740/Kconfig | 6 ++
> 2 files changed, 189 insertions(+)
> create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
>
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> new file mode 100644
> index 00000000..02a9b2a
> --- /dev/null
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -0,0 +1,183 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/clock/x1000-cgu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ingenic,x1000", "ingenic,x1000e";
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + intc: interrupt-controller@10001000 {
> + compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
> + reg = <0x10001000 0x50>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + exclk: ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + rtclk: rtc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + cgu: x1000-cgu@10000000 {
> + compatible = "ingenic,x1000-cgu";
> + reg = <0x10000000 0x100>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&exclk>, <&rtclk>;
> + clock-names = "ext", "rtc";
> + };
> +
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <>;
You can drop the 'apb' node and list the children in the top node
directly. That's what we do in the devicetree for the other Ingenic
SoCs.
Cheers,
-Paul
> +
> + tcu: timer@10002000 {
> + compatible = "ingenic,x1000-tcu",
> + "ingenic,jz4770-tcu",
> + "simple-mfd";
> + reg = <0x10002000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x10002000 0x1000>;
> +
> + #clock-cells = <1>;
> +
> + clocks = <&cgu X1000_CLK_RTCLK
> + &cgu X1000_CLK_EXCLK
> + &cgu X1000_CLK_PCLK>;
> + clock-names = "rtc", "ext", "pclk";
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <27 26 25>;
> + };
> +
> + uart0: serial@10030000 {
> + compatible = "ingenic,x1000-uart";
> + reg = <0x10030000 0x100>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <51>;
> +
> + clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
> + clock-names = "baud", "module";
> +
> + status = "disabled";
> + };
> +
> + uart1: serial@10031000 {
> + compatible = "ingenic,x1000-uart";
> + reg = <0x10031000 0x100>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <50>;
> +
> + clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
> + clock-names = "baud", "module";
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@10032000 {
> + compatible = "ingenic,x1000-uart";
> + reg = <0x10032000 0x100>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <49>;
> +
> + clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
> + clock-names = "baud", "module";
> +
> + status = "disabled";
> + };
> +
> + pinctrl: pin-controller@10010000 {
> + compatible = "ingenic,x1000-pinctrl";
> + reg = <0x10010000 0x800>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpa: gpio@0 {
> + compatible = "ingenic,x1000-gpio";
> + reg = <0>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <17>;
> + };
> +
> + gpb: gpio@1 {
> + compatible = "ingenic,x1000-gpio";
> + reg = <1>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <16>;
> + };
> +
> + gpc: gpio@2 {
> + compatible = "ingenic,x1000-gpio";
> + reg = <2>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <15>;
> + };
> +
> + gpd: gpio@3 {
> + compatible = "ingenic,x1000-gpio";
> + reg = <3>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <14>;
> + };
> + };
> + };
> +};
> diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
> index 4dd0c44..6b96844 100644
> --- a/arch/mips/jz4740/Kconfig
> +++ b/arch/mips/jz4740/Kconfig
> @@ -33,3 +33,9 @@ config MACH_JZ4780
> select MIPS_CPU_SCACHE
> select SYS_HAS_CPU_MIPS32_R2
> select SYS_SUPPORTS_HIGHMEM
> +
> +config MACH_X1000
> + bool
> + select MIPS_CPU_SCACHE
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_SUPPORTS_HIGHMEM
> --
> 2.7.4
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support.
2019-11-24 13:09 ` Paul Cercueil
@ 2019-11-24 14:41 ` Zhou Yanjie
0 siblings, 0 replies; 7+ messages in thread
From: Zhou Yanjie @ 2019-11-24 14:41 UTC (permalink / raw
To: Paul Cercueil
Cc: linux-mips, linux-kernel, devicetree, robh+dt, paul.burton,
paulburton, jhogan, mripard, shawnguo, mark.rutland, syq, ralf,
heiko, icenowy, laurent.pinchart, krzk, geert+renesas,
prasannatsmkumar, sernia.zhou, zhenwenjin, 772753199
Hi Paul,
On 2019年11月24日 21:09, Paul Cercueil wrote:
> Hi Zhou,
>
>
> Le sam., nov. 23, 2019 at 10:32, Zhou Yanjie <zhouyanjie@zoho.com> a
> écrit :
>> Support the Ingenic X1000 SoC using the code under arch/mips/jz4740.
>> This is left unselectable in Kconfig until a X1000 based board is
>> added in a later commit.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>>
>> Notes:
>> v1->v2:
>> Rebase on top of mips-next, use ingenic-timer driver
>> for system timer and clocksource.
>>
>> arch/mips/boot/dts/ingenic/x1000.dtsi | 183
>> ++++++++++++++++++++++++++++++++++
>> arch/mips/jz4740/Kconfig | 6 ++
>> 2 files changed, 189 insertions(+)
>> create mode 100644 arch/mips/boot/dts/ingenic/x1000.dtsi
>>
>> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
>> b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> new file mode 100644
>> index 00000000..02a9b2a
>> --- /dev/null
>> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
>> @@ -0,0 +1,183 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include <dt-bindings/clock/x1000-cgu.h>
>> +
>> +/ {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "ingenic,x1000", "ingenic,x1000e";
>> +
>> + cpuintc: interrupt-controller {
>> + #address-cells = <0>;
>> + #interrupt-cells = <1>;
>> + interrupt-controller;
>> + compatible = "mti,cpu-interrupt-controller";
>> + };
>> +
>> + intc: interrupt-controller@10001000 {
>> + compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
>> + reg = <0x10001000 0x50>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + interrupt-parent = <&cpuintc>;
>> + interrupts = <2>;
>> + };
>> +
>> + exclk: ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + rtclk: rtc {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32768>;
>> + };
>> +
>> + cgu: x1000-cgu@10000000 {
>> + compatible = "ingenic,x1000-cgu";
>> + reg = <0x10000000 0x100>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&exclk>, <&rtclk>;
>> + clock-names = "ext", "rtc";
>> + };
>> +
>> + apb {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <>;
>
> You can drop the 'apb' node and list the children in the top node
> directly. That's what we do in the devicetree for the other Ingenic SoCs.
>
Sure, I'll drop it in v2.
Thanks and best regards!
> Cheers,
> -Paul
>
>
>> +
>> + tcu: timer@10002000 {
>> + compatible = "ingenic,x1000-tcu",
>> + "ingenic,jz4770-tcu",
>> + "simple-mfd";
>> + reg = <0x10002000 0x1000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x10002000 0x1000>;
>> +
>> + #clock-cells = <1>;
>> +
>> + clocks = <&cgu X1000_CLK_RTCLK
>> + &cgu X1000_CLK_EXCLK
>> + &cgu X1000_CLK_PCLK>;
>> + clock-names = "rtc", "ext", "pclk";
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <27 26 25>;
>> + };
>> +
>> + uart0: serial@10030000 {
>> + compatible = "ingenic,x1000-uart";
>> + reg = <0x10030000 0x100>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <51>;
>> +
>> + clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
>> + clock-names = "baud", "module";
>> +
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@10031000 {
>> + compatible = "ingenic,x1000-uart";
>> + reg = <0x10031000 0x100>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <50>;
>> +
>> + clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
>> + clock-names = "baud", "module";
>> +
>> + status = "disabled";
>> + };
>> +
>> + uart2: serial@10032000 {
>> + compatible = "ingenic,x1000-uart";
>> + reg = <0x10032000 0x100>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <49>;
>> +
>> + clocks = <&exclk>, <&cgu X1000_CLK_UART2>;
>> + clock-names = "baud", "module";
>> +
>> + status = "disabled";
>> + };
>> +
>> + pinctrl: pin-controller@10010000 {
>> + compatible = "ingenic,x1000-pinctrl";
>> + reg = <0x10010000 0x800>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + gpa: gpio@0 {
>> + compatible = "ingenic,x1000-gpio";
>> + reg = <0>;
>> +
>> + gpio-controller;
>> + gpio-ranges = <&pinctrl 0 0 32>;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <17>;
>> + };
>> +
>> + gpb: gpio@1 {
>> + compatible = "ingenic,x1000-gpio";
>> + reg = <1>;
>> +
>> + gpio-controller;
>> + gpio-ranges = <&pinctrl 0 32 32>;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <16>;
>> + };
>> +
>> + gpc: gpio@2 {
>> + compatible = "ingenic,x1000-gpio";
>> + reg = <2>;
>> +
>> + gpio-controller;
>> + gpio-ranges = <&pinctrl 0 64 32>;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <15>;
>> + };
>> +
>> + gpd: gpio@3 {
>> + compatible = "ingenic,x1000-gpio";
>> + reg = <3>;
>> +
>> + gpio-controller;
>> + gpio-ranges = <&pinctrl 0 96 32>;
>> + #gpio-cells = <2>;
>> +
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> +
>> + interrupt-parent = <&intc>;
>> + interrupts = <14>;
>> + };
>> + };
>> + };
>> +};
>> diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
>> index 4dd0c44..6b96844 100644
>> --- a/arch/mips/jz4740/Kconfig
>> +++ b/arch/mips/jz4740/Kconfig
>> @@ -33,3 +33,9 @@ config MACH_JZ4780
>> select MIPS_CPU_SCACHE
>> select SYS_HAS_CPU_MIPS32_R2
>> select SYS_SUPPORTS_HIGHMEM
>> +
>> +config MACH_X1000
>> + bool
>> + select MIPS_CPU_SCACHE
>> + select SYS_HAS_CPU_MIPS32_R2
>> + select SYS_SUPPORTS_HIGHMEM
>> --
>> 2.7.4
>>
>>
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-24 14:42 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-11-23 2:32 Add initial support for Ingenic X1000 SoC and Y&A CU Neo board v2 Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 1/4] MIPS: Ingenic: initial X1000 support Zhou Yanjie
2019-11-24 13:09 ` Paul Cercueil
2019-11-24 14:41 ` Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 2/4] dt-bindings: Document yna vendor-prefix Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 3/4] dt-bindings: MIPS: Add Ingenic XBurst based boards Zhou Yanjie
2019-11-23 2:32 ` [PATCH v2 4/4] MIPS: Ingenic: Initial YSH & ATIL CU Neo board. support Zhou Yanjie
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