* [PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
@ 2020-11-13 3:02 SkyLake Huang
2020-11-13 3:02 ` [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller SkyLake Huang
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: SkyLake Huang @ 2020-11-13 3:02 UTC (permalink / raw
To: u-boot
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
This patch adds support MTK's SPI NOR controller on
mt7622 & mt7629. With this controller, you can access
SPI NOR with better performance on mt762x platform.
SkyLake.Huang (2):
spi: mtk_snor: add support for MTK SPI NOR controller
arm: dts: enable MTK SPI NOR controller driver
arch/arm/dts/mt7622-rfb.dts | 14 +-
arch/arm/dts/mt7622.dtsi | 7 +
arch/arm/dts/mt7629-rfb.dts | 14 +-
arch/arm/dts/mt7629.dtsi | 9 +
configs/mt7622_rfb_defconfig | 3 +-
configs/mt7629_rfb_defconfig | 3 +-
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mtk_snor.c | 597 +++++++++++++++++++++++++++++++++++
9 files changed, 651 insertions(+), 4 deletions(-)
create mode 100644 drivers/spi/mtk_snor.c
--
2.18.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller
2020-11-13 3:02 [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
@ 2020-11-13 3:02 ` SkyLake Huang
2020-12-07 17:48 ` Jagan Teki
2020-11-13 3:02 ` [PATCH 2/2] arm: dts: enable MTK SPI NOR controller driver SkyLake Huang
2020-11-26 3:54 ` [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
2 siblings, 1 reply; 7+ messages in thread
From: SkyLake Huang @ 2020-11-13 3:02 UTC (permalink / raw
To: u-boot
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
This patch adds support for MTK SPI NOR controller, which you
can see on mt7622 & mt7629.
This controller is designed only for SPI NOR. We can't adjust
its bus clock dynamically. Set clock in dts instead.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mtk_snor.c | 597 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 605 insertions(+)
create mode 100644 drivers/spi/mtk_snor.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index fae2040af8..670af450c1 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -174,6 +174,13 @@ config MT7621_SPI
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
+config MTK_SNOR
+ bool "Mediatek SPI-NOR controller driver"
+ depends on SPI_MEM
+ help
+ Enable the Mediatek SPINOR controller driver. This driver has
+ better read/write performance with NOR.
+
config MTK_SNFI_SPI
bool "Mediatek SPI memory controller driver"
depends on SPI_MEM
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index ae4f2958f8..efe92f6b18 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
+obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
new file mode 100644
index 0000000000..0a92f1c5a8
--- /dev/null
+++ b/drivers/spi/mtk_snor.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Mediatek SPI-NOR controller driver
+//
+// Copyright (C) 2020 SkyLake Huang <SkyLake.Huang@mediatek.com>
+//
+// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
+
+#include <common.h>
+#include <clk.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <errno.h>
+#include <spi.h>
+#include <spi-mem.h>
+#include <stdbool.h>
+#include <watchdog.h>
+#include <dm/pinctrl.h>
+#include <dm/device.h>
+#include <asm/dma-mapping.h>
+#include <linux/dma-direction.h>
+#include <linux/completion.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+
+#define DRIVER_NAME "mtk-spi-nor"
+
+#define MTK_NOR_REG_CMD 0x00
+#define MTK_NOR_CMD_WRSR BIT(5)
+#define MTK_NOR_CMD_WRITE BIT(4)
+#define MTK_NOR_CMD_PROGRAM BIT(2)
+#define MTK_NOR_CMD_RDSR BIT(1)
+#define MTK_NOR_CMD_READ BIT(0)
+#define MTK_NOR_CMD_MASK GENMASK(5, 0)
+
+#define MTK_NOR_REG_PRG_CNT 0x04
+#define MTK_NOR_REG_RDSR 0x08
+#define MTK_NOR_REG_RDATA 0x0c
+
+#define MTK_NOR_REG_RADR0 0x10
+#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
+#define MTK_NOR_REG_RADR3 0xc8
+
+#define MTK_NOR_REG_WDATA 0x1c
+
+#define MTK_NOR_REG_PRGDATA0 0x20
+#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
+#define MTK_NOR_REG_PRGDATA_MAX 5
+
+#define MTK_NOR_REG_SHIFT0 0x38
+#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
+#define MTK_NOR_REG_SHIFT_MAX 9
+
+#define MTK_NOR_REG_CFG1 0x60
+#define MTK_NOR_FAST_READ BIT(0)
+
+#define MTK_NOR_REG_CFG2 0x64
+#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
+#define MTK_NOR_WR_BUF_EN BIT(0)
+
+#define MTK_NOR_REG_PP_DATA 0x98
+
+#define MTK_NOR_REG_IRQ_STAT 0xa8
+#define MTK_NOR_REG_IRQ_EN 0xac
+#define MTK_NOR_IRQ_DMA BIT(7)
+#define MTK_NOR_IRQ_WRSR BIT(5)
+#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
+
+#define MTK_NOR_REG_CFG3 0xb4
+#define MTK_NOR_DISABLE_WREN BIT(7)
+#define MTK_NOR_DISABLE_SR_POLL BIT(5)
+
+#define MTK_NOR_REG_WP 0xc4
+#define MTK_NOR_ENABLE_SF_CMD 0x30
+
+#define MTK_NOR_REG_BUSCFG 0xcc
+#define MTK_NOR_4B_ADDR BIT(4)
+#define MTK_NOR_QUAD_ADDR BIT(3)
+#define MTK_NOR_QUAD_READ BIT(2)
+#define MTK_NOR_DUAL_ADDR BIT(1)
+#define MTK_NOR_DUAL_READ BIT(0)
+#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
+
+#define MTK_NOR_REG_DMA_CTL 0x718
+#define MTK_NOR_DMA_START BIT(0)
+
+#define MTK_NOR_REG_DMA_FADR 0x71c
+#define MTK_NOR_REG_DMA_DADR 0x720
+#define MTK_NOR_REG_DMA_END_DADR 0x724
+
+#define MTK_NOR_PRG_MAX_SIZE 6
+// Reading DMA src/dst addresses have to be 16-byte aligned
+#define MTK_NOR_DMA_ALIGN 16
+#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
+// and we allocate a bounce buffer if destination address isn't aligned.
+#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
+
+// Buffered page program can do one 128-byte transfer
+#define MTK_NOR_PP_SIZE 128
+
+#define CLK_TO_US(priv, clkcnt) ((clkcnt) * (1000000) / ((priv)->spi_freq))
+
+#define MTK_NOR_UNLOCK_ALL 0x0
+
+struct mtk_snor_priv {
+ struct device *dev;
+ void __iomem *base;
+ u8 *buffer;
+ struct clk spi_clk;
+ struct clk ctlr_clk;
+ unsigned int spi_freq;
+ bool wbuf_en;
+};
+
+static inline dma_addr_t __dma_map_single(void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ unsigned long addr = (unsigned long)vaddr;
+
+ len = ALIGN(len, ARCH_DMA_MINALIGN);
+ if (dir == DMA_FROM_DEVICE)
+ invalidate_dcache_range(addr, addr + len);
+ else
+ flush_dcache_range(addr, addr + len);
+
+ return addr;
+}
+
+static inline void __dma_unmap_single(dma_addr_t addr, size_t len,
+ enum dma_data_direction dir)
+{
+ len = ALIGN(len, ARCH_DMA_MINALIGN);
+ if (dir != DMA_TO_DEVICE)
+ invalidate_dcache_range(addr, addr + len);
+}
+
+static inline void mtk_snor_rmw(struct mtk_snor_priv *priv, u32 reg, u32 set,
+ u32 clr)
+{
+ u32 val = readl(priv->base + reg);
+
+ val &= ~clr;
+ val |= set;
+ writel(val, priv->base + reg);
+}
+
+static inline int mtk_snor_cmd_exec(struct mtk_snor_priv *priv, u32 cmd,
+ ulong clk)
+{
+ unsigned long long delay = CLK_TO_US(priv, clk);
+ u32 reg;
+ int ret;
+
+ writel(cmd, priv->base + MTK_NOR_REG_CMD);
+
+ delay = (delay + 1) * 200;
+ ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
+ delay);
+ if (ret < 0)
+ dev_err(priv->dev, "command %u timeout.\n", cmd);
+ return ret;
+}
+
+static void mtk_snor_set_addr(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ u32 addr = op->addr.val;
+ int i;
+
+ for (i = 0; i < 3; i++) {
+ writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
+ addr >>= 8;
+ }
+ if (op->addr.nbytes == 4) {
+ writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
+ mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
+ } else {
+ mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
+ }
+}
+
+static bool mtk_snor_match_read(const struct spi_mem_op *op)
+{
+ int dummy = 0;
+
+ if (op->dummy.buswidth)
+ dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
+
+ if (op->data.buswidth == 2 || op->data.buswidth == 4) {
+ if (op->addr.buswidth == 1)
+ return dummy == 8;
+ else if (op->addr.buswidth == 2)
+ return dummy == 4;
+ else if (op->addr.buswidth == 4)
+ return dummy == 6;
+ } else if ((op->addr.buswidth == 0) && (op->data.buswidth == 1)) {
+ return dummy == 0;
+ } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
+ if (op->cmd.opcode == 0x03)
+ return dummy == 0;
+ else if (op->cmd.opcode == 0x0b)
+ return dummy == 8;
+ }
+ return false;
+}
+
+static int mtk_snor_adjust_op_size(struct spi_slave *slave,
+ struct spi_mem_op *op)
+{
+ if (!op->data.nbytes)
+ return 0;
+
+ if (op->addr.nbytes == 3 || op->addr.nbytes == 4) {
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ mtk_snor_match_read(op)) {
+ if (op->addr.val & MTK_NOR_DMA_ALIGN_MASK ||
+ op->data.nbytes < MTK_NOR_DMA_ALIGN)
+ op->data.nbytes = 1;
+ else if (!((ulong)(op->data.buf.in) &
+ MTK_NOR_DMA_ALIGN_MASK))
+ op->data.nbytes &= ~MTK_NOR_DMA_ALIGN_MASK;
+ else if (op->data.nbytes > MTK_NOR_BOUNCE_BUF_SIZE)
+ op->data.nbytes = MTK_NOR_BOUNCE_BUF_SIZE;
+ return 0;
+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ if (op->data.nbytes >= MTK_NOR_PP_SIZE)
+ op->data.nbytes = MTK_NOR_PP_SIZE;
+ else
+ op->data.nbytes = 1;
+ return 0;
+ }
+ }
+
+ return 0;
+}
+
+static bool mtk_snor_supports_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ size_t len;
+
+ if (op->cmd.buswidth != 1)
+ return false;
+
+ if (op->addr.nbytes == 3 || op->addr.nbytes == 4) {
+ if (op->data.dir == SPI_MEM_DATA_IN &&
+ mtk_snor_match_read(op))
+ return true;
+ else if (op->data.dir == SPI_MEM_DATA_OUT)
+ return (op->addr.buswidth == 1) &&
+ (op->dummy.buswidth == 0) &&
+ (op->data.buswidth == 1);
+ }
+ len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ if (len > MTK_NOR_PRG_MAX_SIZE ||
+ (op->data.nbytes && len == MTK_NOR_PRG_MAX_SIZE))
+ return false;
+ return true;
+}
+
+static void mtk_snor_setup_bus(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ u32 reg = 0;
+
+ if (op->addr.nbytes == 4)
+ reg |= MTK_NOR_4B_ADDR;
+
+ if (op->data.buswidth == 4) {
+ reg |= MTK_NOR_QUAD_READ;
+ writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(4));
+ if (op->addr.buswidth == 4)
+ reg |= MTK_NOR_QUAD_ADDR;
+ } else if (op->data.buswidth == 2) {
+ reg |= MTK_NOR_DUAL_READ;
+ writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA(3));
+ if (op->addr.buswidth == 2)
+ reg |= MTK_NOR_DUAL_ADDR;
+ } else {
+ if (op->cmd.opcode == 0x0b)
+ mtk_snor_rmw(priv, MTK_NOR_REG_CFG1,
+ MTK_NOR_FAST_READ, 0);
+ else
+ mtk_snor_rmw(priv, MTK_NOR_REG_CFG1,
+ 0, MTK_NOR_FAST_READ);
+ }
+ mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, reg, MTK_NOR_BUS_MODE_MASK);
+}
+
+static int mtk_snor_read_dma(struct mtk_snor_priv *priv, u32 from,
+ unsigned int length, u8 *buffer)
+{
+ int ret = 0;
+ ulong delay;
+ u32 reg;
+ dma_addr_t dma_addr;
+
+ dma_addr = __dma_map_single(buffer, length, DMA_FROM_DEVICE);
+ if (dma_mapping_error(priv->dev, dma_addr)) {
+ dev_err(priv->dev, "failed to map dma buffer.\n");
+ return -EINVAL;
+ }
+
+ writel(from, priv->base + MTK_NOR_REG_DMA_FADR);
+ writel(dma_addr, priv->base + MTK_NOR_REG_DMA_DADR);
+ writel(dma_addr + length, priv->base + MTK_NOR_REG_DMA_END_DADR);
+
+ mtk_snor_rmw(priv, MTK_NOR_REG_DMA_CTL, MTK_NOR_DMA_START, 0);
+
+ delay = CLK_TO_US(priv, ((u64)length + 5) * BITS_PER_BYTE);
+
+ delay = (delay + 1) * 100;
+ ret = readl_poll_timeout(priv->base + MTK_NOR_REG_DMA_CTL, reg,
+ !(reg & MTK_NOR_DMA_START),
+ delay);
+
+ __dma_unmap_single(dma_addr, length, DMA_FROM_DEVICE);
+ if (ret < 0)
+ dev_err(priv->dev, "dma read timeout.\n");
+
+ return ret;
+}
+
+static int mtk_snor_read_bounce(struct mtk_snor_priv *priv, u32 from,
+ unsigned int length, u8 *buffer)
+{
+ unsigned int rdlen;
+ int ret;
+
+ if (length & MTK_NOR_DMA_ALIGN_MASK)
+ rdlen = (length + MTK_NOR_DMA_ALIGN) & ~MTK_NOR_DMA_ALIGN_MASK;
+ else
+ rdlen = length;
+
+ ret = mtk_snor_read_dma(priv, from, rdlen, priv->buffer);
+ if (ret)
+ return ret;
+
+ memcpy(buffer, priv->buffer, length);
+ return 0;
+}
+
+static int mtk_snor_read_pio(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ u8 *buf = op->data.buf.in;
+ int ret;
+
+ ret = mtk_snor_cmd_exec(priv, MTK_NOR_CMD_READ, 6 * BITS_PER_BYTE);
+ if (!ret)
+ buf[0] = readb(priv->base + MTK_NOR_REG_RDATA);
+ return ret;
+}
+
+static int mtk_snor_write_buffer_enable(struct mtk_snor_priv *priv)
+{
+ int ret;
+ u32 val;
+
+ if (priv->wbuf_en)
+ return 0;
+
+ val = readl(priv->base + MTK_NOR_REG_CFG2);
+ writel(val | MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
+ ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
+ val & MTK_NOR_WR_BUF_EN, 10000);
+ if (!ret)
+ priv->wbuf_en = true;
+ return ret;
+}
+
+static int mtk_snor_write_buffer_disable(struct mtk_snor_priv *priv)
+{
+ int ret;
+ u32 val;
+
+ if (!priv->wbuf_en)
+ return 0;
+ val = readl(priv->base + MTK_NOR_REG_CFG2);
+ writel(val & ~MTK_NOR_WR_BUF_EN, priv->base + MTK_NOR_REG_CFG2);
+ ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CFG2, val,
+ !(val & MTK_NOR_WR_BUF_EN), 10000);
+ if (!ret)
+ priv->wbuf_en = false;
+ return ret;
+}
+
+static int mtk_snor_pp_buffered(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ const u8 *buf = op->data.buf.out;
+ u32 val;
+ int ret, i;
+
+ ret = mtk_snor_write_buffer_enable(priv);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < op->data.nbytes; i += 4) {
+ val = buf[i + 3] << 24 | buf[i + 2] << 16 | buf[i + 1] << 8 |
+ buf[i];
+ writel(val, priv->base + MTK_NOR_REG_PP_DATA);
+ }
+ mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE,
+ (op->data.nbytes + 5) * BITS_PER_BYTE);
+ return mtk_snor_write_buffer_disable(priv);
+}
+
+static int mtk_snor_pp_unbuffered(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ const u8 *buf = op->data.buf.out;
+ int ret;
+
+ ret = mtk_snor_write_buffer_disable(priv);
+ if (ret < 0)
+ return ret;
+ writeb(buf[0], priv->base + MTK_NOR_REG_WDATA);
+ return mtk_snor_cmd_exec(priv, MTK_NOR_CMD_WRITE, 6 * BITS_PER_BYTE);
+}
+
+static int mtk_nor_cmd_program(struct mtk_snor_priv *priv,
+ const struct spi_mem_op *op)
+{
+ u32 tx_len = 0;
+ u32 trx_len = 0;
+ int reg_offset = MTK_NOR_REG_PRGDATA_MAX;
+ void __iomem *reg;
+ u8 *txbuf;
+ int tx_cnt = 0;
+ u8 *rxbuf = op->data.buf.in;
+ int i = 0;
+
+ tx_len = 1 + op->addr.nbytes + op->dummy.nbytes;
+ trx_len = tx_len + op->data.nbytes;
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ tx_len += op->data.nbytes;
+
+ txbuf = malloc(tx_len * sizeof(u8));
+ memset(txbuf, 0x0, tx_len * sizeof(u8));
+
+ /* Join all bytes to be transferred */
+ txbuf[tx_cnt] = op->cmd.opcode;
+ tx_cnt++;
+ for (i = op->addr.nbytes; i > 0; i--, tx_cnt++)
+ txbuf[tx_cnt] = ((u8 *)&op->addr.val)[i - 1];
+ for (i = op->dummy.nbytes; i > 0; i--, tx_cnt++)
+ txbuf[tx_cnt] = 0x0;
+ if (op->data.dir == SPI_MEM_DATA_OUT)
+ for (i = op->data.nbytes; i > 0; i--, tx_cnt++)
+ txbuf[tx_cnt] = ((u8 *)op->data.buf.out)[i - 1];
+
+ for (i = MTK_NOR_REG_PRGDATA_MAX; i >= 0; i--)
+ writeb(0, priv->base + MTK_NOR_REG_PRGDATA(i));
+
+ for (i = 0; i < tx_len; i++, reg_offset--)
+ writeb(txbuf[i], priv->base + MTK_NOR_REG_PRGDATA(reg_offset));
+
+ writel(trx_len * BITS_PER_BYTE, priv->base + MTK_NOR_REG_PRG_CNT);
+
+ mtk_snor_cmd_exec(priv, MTK_NOR_CMD_PROGRAM, trx_len * BITS_PER_BYTE);
+
+ reg_offset = op->data.nbytes - 1;
+ for (i = 0; i < op->data.nbytes; i++, reg_offset--) {
+ reg = priv->base + MTK_NOR_REG_SHIFT(reg_offset);
+ rxbuf[i] = readb(reg);
+ }
+
+ return 0;
+}
+
+static int mtk_snor_exec_op(struct spi_slave *slave,
+ const struct spi_mem_op *op)
+{
+ struct udevice *bus = dev_get_parent(slave->dev);
+ struct mtk_snor_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ if (op->addr.nbytes == 0 || op->cmd.opcode == 0xd8) {
+ return mtk_nor_cmd_program(priv, op);
+ } else if (op->data.dir == SPI_MEM_DATA_OUT) {
+ mtk_snor_set_addr(priv, op);
+ writeb(op->cmd.opcode, priv->base + MTK_NOR_REG_PRGDATA0);
+ if (op->data.nbytes == MTK_NOR_PP_SIZE)
+ return mtk_snor_pp_buffered(priv, op);
+ return mtk_snor_pp_unbuffered(priv, op);
+ } else if ((op->data.dir == SPI_MEM_DATA_IN) &&
+ mtk_snor_match_read(op)) {
+ ret = mtk_snor_write_buffer_disable(priv);
+ if (ret < 0)
+ return ret;
+ mtk_snor_setup_bus(priv, op);
+ if (op->data.nbytes == 1) {
+ mtk_snor_set_addr(priv, op);
+ return mtk_snor_read_pio(priv, op);
+ } else if (((ulong)(op->data.buf.in) &
+ MTK_NOR_DMA_ALIGN_MASK)) {
+ return mtk_snor_read_bounce(priv, op->addr.val,
+ op->data.nbytes,
+ op->data.buf.in);
+ } else {
+ return mtk_snor_read_dma(priv, op->addr.val,
+ op->data.nbytes,
+ op->data.buf.in);
+ }
+ }
+
+ return -ENOTSUPP;
+}
+
+static int mtk_snor_probe(struct udevice *bus)
+{
+ struct mtk_snor_priv *priv = dev_get_priv(bus);
+ u8 *buffer;
+ int ret;
+
+ priv->base = (void __iomem *)devfdt_get_addr(bus);
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_name(bus, "spi", &priv->spi_clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_get_by_name(bus, "sf", &priv->ctlr_clk);
+ if (ret < 0)
+ return ret;
+
+ buffer = devm_kmalloc(bus,
+ MTK_NOR_BOUNCE_BUF_SIZE + MTK_NOR_DMA_ALIGN,
+ GFP_KERNEL);
+ if (!buffer)
+ return -ENOMEM;
+ if ((ulong)buffer & MTK_NOR_DMA_ALIGN_MASK)
+ buffer = (u8 *)(((ulong)buffer + MTK_NOR_DMA_ALIGN) &
+ ~MTK_NOR_DMA_ALIGN_MASK);
+ priv->buffer = buffer;
+
+ clk_enable(&priv->spi_clk);
+ clk_enable(&priv->ctlr_clk);
+
+ priv->spi_freq = clk_get_rate(&priv->spi_clk);
+ printf("spi frequency: %d Hz\n", priv->spi_freq);
+
+ /* With this setting, we issue one command at a time to
+ * accommodate to SPI-mem framework.
+ */
+ writel(MTK_NOR_ENABLE_SF_CMD, priv->base + MTK_NOR_REG_WP);
+ mtk_snor_rmw(priv, MTK_NOR_REG_CFG2, MTK_NOR_WR_CUSTOM_OP_EN, 0);
+ mtk_snor_rmw(priv, MTK_NOR_REG_CFG3,
+ MTK_NOR_DISABLE_WREN | MTK_NOR_DISABLE_SR_POLL, 0);
+
+ return 0;
+}
+
+static int mtk_snor_set_speed(struct udevice *bus, uint speed)
+{
+ /* MTK's SNOR controller does not have a bus clock divider.
+ * We setup maximum bus clock in dts.
+ */
+
+ return 0;
+}
+
+static int mtk_snor_set_mode(struct udevice *bus, uint mode)
+{
+ /* We set up mode later for each transmission.
+ */
+ return 0;
+}
+
+static const struct spi_controller_mem_ops mtk_snor_mem_ops = {
+ .adjust_op_size = mtk_snor_adjust_op_size,
+ .supports_op = mtk_snor_supports_op,
+ .exec_op = mtk_snor_exec_op
+};
+
+static const struct dm_spi_ops mtk_snor_ops = {
+ .mem_ops = &mtk_snor_mem_ops,
+ .set_speed = mtk_snor_set_speed,
+ .set_mode = mtk_snor_set_mode,
+};
+
+static const struct udevice_id mtk_snor_ids[] = {
+ { .compatible = "mediatek,mtk-snor"},
+ { }
+};
+
+U_BOOT_DRIVER(mtk_snor) = {
+ .name = "mtk_snor",
+ .id = UCLASS_SPI,
+ .of_match = mtk_snor_ids,
+ .ops = &mtk_snor_ops,
+ .priv_auto_alloc_size = sizeof(struct mtk_snor_priv),
+ .probe = mtk_snor_probe,
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] arm: dts: enable MTK SPI NOR controller driver
2020-11-13 3:02 [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
2020-11-13 3:02 ` [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller SkyLake Huang
@ 2020-11-13 3:02 ` SkyLake Huang
2020-11-26 3:54 ` [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
2 siblings, 0 replies; 7+ messages in thread
From: SkyLake Huang @ 2020-11-13 3:02 UTC (permalink / raw
To: u-boot
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
Enable MTK SPI NOR controller driver on mt7622 & mt7629.
Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
---
arch/arm/dts/mt7622-rfb.dts | 14 +++++++++++++-
arch/arm/dts/mt7622.dtsi | 7 +++++++
arch/arm/dts/mt7629-rfb.dts | 14 +++++++++++++-
arch/arm/dts/mt7629.dtsi | 9 +++++++++
configs/mt7622_rfb_defconfig | 3 ++-
configs/mt7629_rfb_defconfig | 3 ++-
6 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index 52b34fa3b3..9322c54a3c 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -19,7 +19,7 @@
};
aliases {
- spi0 = &snfi;
+ spi0 = &snor;
};
memory at 40000000 {
@@ -151,6 +151,18 @@
quad-spi;
};
+&snor {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snor_pins>;
+ status = "okay";
+
+ spi-flash at 0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index e511432da9..53d24ac63d 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -68,7 +68,14 @@
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
<&topckgen CLK_TOP_UNIVPLL2_D8>;
+ };
+ snor: snor at 11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
status = "disabled";
};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 687fe1c029..c75c4c7a38 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -14,7 +14,7 @@
compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
aliases {
- spi0 = &snfi;
+ spi0 = &snor;
};
chosen {
@@ -76,6 +76,18 @@
};
};
+&snor {
+ pinctrl-names = "default";
+ pinctrl-0 = <&snor_pins>;
+ status = "okay";
+
+ spi-flash at 0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index a33a74a556..b268db7498 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -222,6 +222,15 @@
#size-cells = <0>;
};
+ snor: snor at 11014000 {
+ compatible = "mediatek,mtk-snor";
+ reg = <0x11014000 0x1000>;
+ clocks = <&pericfg CLK_PERI_FLASH_PD>,
+ <&topckgen CLK_TOP_FLASH_SEL>;
+ clock-names = "spi", "sf";
+ status = "disabled";
+ };
+
ethsys: syscon at 1b000000 {
compatible = "mediatek,mt7629-ethsys", "syscon";
reg = <0x1b000000 0x1000>;
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index ae5fda52d7..4747470f08 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -54,7 +54,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TIMER=y
CONFIG_MTK_TIMER=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index 9b94c2038e..b5a5059998 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -65,7 +65,8 @@ CONFIG_DM_SERIAL=y
CONFIG_MTK_SERIAL=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
-CONFIG_MTK_SNFI_SPI=y
+# CONFIG_MTK_SNFI_SPI is not set
+CONFIG_MTK_SNOR=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
--
2.18.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
2020-11-13 3:02 [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
2020-11-13 3:02 ` [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller SkyLake Huang
2020-11-13 3:02 ` [PATCH 2/2] arm: dts: enable MTK SPI NOR controller driver SkyLake Huang
@ 2020-11-26 3:54 ` SkyLake Huang
2 siblings, 0 replies; 7+ messages in thread
From: SkyLake Huang @ 2020-11-26 3:54 UTC (permalink / raw
To: u-boot
HiJagan,
On Fri, 2020-11-13 at 11:02 +0800, SkyLake Huang wrote:
> From: "SkyLake.Huang" <skylake.huang@mediatek.com>
>
> This patch adds support MTK's SPI NOR controller on
> mt7622 & mt7629. With this controller, you can access
> SPI NOR with better performance on mt762x platform.
>
> SkyLake.Huang (2):
> spi: mtk_snor: add support for MTK SPI NOR controller
> arm: dts: enable MTK SPI NOR controller driver
>
> arch/arm/dts/mt7622-rfb.dts | 14 +-
> arch/arm/dts/mt7622.dtsi | 7 +
> arch/arm/dts/mt7629-rfb.dts | 14 +-
> arch/arm/dts/mt7629.dtsi | 9 +
> configs/mt7622_rfb_defconfig | 3 +-
> configs/mt7629_rfb_defconfig | 3 +-
> drivers/spi/Kconfig | 7 +
> drivers/spi/Makefile | 1 +
> drivers/spi/mtk_snor.c | 597 +++++++++++++++++++++++++++++++++++
> 9 files changed, 651 insertions(+), 4 deletions(-)
> create mode 100644 drivers/spi/mtk_snor.c
>
A gentle ping.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller
2020-11-13 3:02 ` [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller SkyLake Huang
@ 2020-12-07 17:48 ` Jagan Teki
2021-01-18 4:19 ` SkyLake Huang
0 siblings, 1 reply; 7+ messages in thread
From: Jagan Teki @ 2020-12-07 17:48 UTC (permalink / raw
To: u-boot
On Fri, Nov 13, 2020 at 8:32 AM SkyLake Huang
<SkyLake.Huang@mediatek.com> wrote:
>
> From: "SkyLake.Huang" <skylake.huang@mediatek.com>
>
> This patch adds support for MTK SPI NOR controller, which you
> can see on mt7622 & mt7629.
>
> This controller is designed only for SPI NOR. We can't adjust
> its bus clock dynamically. Set clock in dts instead.
>
> Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
> ---
> drivers/spi/Kconfig | 7 +
> drivers/spi/Makefile | 1 +
> drivers/spi/mtk_snor.c | 597 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 605 insertions(+)
> create mode 100644 drivers/spi/mtk_snor.c
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index fae2040af8..670af450c1 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -174,6 +174,13 @@ config MT7621_SPI
> the SPI NOR flash on platforms embedding this Ralink / MediaTek
> SPI core, like MT7621/7628/7688.
>
> +config MTK_SNOR
> + bool "Mediatek SPI-NOR controller driver"
> + depends on SPI_MEM
> + help
> + Enable the Mediatek SPINOR controller driver. This driver has
> + better read/write performance with NOR.
> +
> config MTK_SNFI_SPI
> bool "Mediatek SPI memory controller driver"
> depends on SPI_MEM
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index ae4f2958f8..efe92f6b18 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -38,6 +38,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
> +obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
> obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
> obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
> obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
> diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
> new file mode 100644
> index 0000000000..0a92f1c5a8
> --- /dev/null
> +++ b/drivers/spi/mtk_snor.c
> @@ -0,0 +1,597 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Mediatek SPI-NOR controller driver
> +//
> +// Copyright (C) 2020 SkyLake Huang <SkyLake.Huang@mediatek.com>
> +//
> +// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
> +
> +#include <common.h>
> +#include <clk.h>
> +#include <cpu_func.h>
> +#include <dm.h>
> +#include <errno.h>
> +#include <spi.h>
> +#include <spi-mem.h>
> +#include <stdbool.h>
> +#include <watchdog.h>
> +#include <dm/pinctrl.h>
> +#include <dm/device.h>
> +#include <asm/dma-mapping.h>
> +#include <linux/dma-direction.h>
> +#include <linux/completion.h>
> +#include <linux/bitops.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +
> +#define DRIVER_NAME "mtk-spi-nor"
> +
> +#define MTK_NOR_REG_CMD 0x00
> +#define MTK_NOR_CMD_WRSR BIT(5)
> +#define MTK_NOR_CMD_WRITE BIT(4)
> +#define MTK_NOR_CMD_PROGRAM BIT(2)
> +#define MTK_NOR_CMD_RDSR BIT(1)
> +#define MTK_NOR_CMD_READ BIT(0)
> +#define MTK_NOR_CMD_MASK GENMASK(5, 0)
> +
> +#define MTK_NOR_REG_PRG_CNT 0x04
> +#define MTK_NOR_REG_RDSR 0x08
> +#define MTK_NOR_REG_RDATA 0x0c
> +
> +#define MTK_NOR_REG_RADR0 0x10
> +#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
> +#define MTK_NOR_REG_RADR3 0xc8
> +
> +#define MTK_NOR_REG_WDATA 0x1c
> +
> +#define MTK_NOR_REG_PRGDATA0 0x20
> +#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
> +#define MTK_NOR_REG_PRGDATA_MAX 5
> +
> +#define MTK_NOR_REG_SHIFT0 0x38
> +#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
> +#define MTK_NOR_REG_SHIFT_MAX 9
> +
> +#define MTK_NOR_REG_CFG1 0x60
> +#define MTK_NOR_FAST_READ BIT(0)
> +
> +#define MTK_NOR_REG_CFG2 0x64
> +#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
> +#define MTK_NOR_WR_BUF_EN BIT(0)
> +
> +#define MTK_NOR_REG_PP_DATA 0x98
> +
> +#define MTK_NOR_REG_IRQ_STAT 0xa8
> +#define MTK_NOR_REG_IRQ_EN 0xac
> +#define MTK_NOR_IRQ_DMA BIT(7)
> +#define MTK_NOR_IRQ_WRSR BIT(5)
> +#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
> +
> +#define MTK_NOR_REG_CFG3 0xb4
> +#define MTK_NOR_DISABLE_WREN BIT(7)
> +#define MTK_NOR_DISABLE_SR_POLL BIT(5)
> +
> +#define MTK_NOR_REG_WP 0xc4
> +#define MTK_NOR_ENABLE_SF_CMD 0x30
> +
> +#define MTK_NOR_REG_BUSCFG 0xcc
> +#define MTK_NOR_4B_ADDR BIT(4)
> +#define MTK_NOR_QUAD_ADDR BIT(3)
> +#define MTK_NOR_QUAD_READ BIT(2)
> +#define MTK_NOR_DUAL_ADDR BIT(1)
> +#define MTK_NOR_DUAL_READ BIT(0)
> +#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
> +
> +#define MTK_NOR_REG_DMA_CTL 0x718
> +#define MTK_NOR_DMA_START BIT(0)
> +
> +#define MTK_NOR_REG_DMA_FADR 0x71c
> +#define MTK_NOR_REG_DMA_DADR 0x720
> +#define MTK_NOR_REG_DMA_END_DADR 0x724
> +
> +#define MTK_NOR_PRG_MAX_SIZE 6
> +// Reading DMA src/dst addresses have to be 16-byte aligned
> +#define MTK_NOR_DMA_ALIGN 16
> +#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
> +// and we allocate a bounce buffer if destination address isn't aligned.
> +#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
> +
> +// Buffered page program can do one 128-byte transfer
> +#define MTK_NOR_PP_SIZE 128
> +
> +#define CLK_TO_US(priv, clkcnt) ((clkcnt) * (1000000) / ((priv)->spi_freq))
> +
> +#define MTK_NOR_UNLOCK_ALL 0x0
> +
> +struct mtk_snor_priv {
> + struct device *dev;
> + void __iomem *base;
> + u8 *buffer;
> + struct clk spi_clk;
> + struct clk ctlr_clk;
> + unsigned int spi_freq;
> + bool wbuf_en;
> +};
> +
> +static inline dma_addr_t __dma_map_single(void *vaddr, size_t len,
> + enum dma_data_direction dir)
> +{
> + unsigned long addr = (unsigned long)vaddr;
> +
> + len = ALIGN(len, ARCH_DMA_MINALIGN);
> + if (dir == DMA_FROM_DEVICE)
> + invalidate_dcache_range(addr, addr + len);
> + else
> + flush_dcache_range(addr, addr + len);
> +
> + return addr;
> +}
> +
> +static inline void __dma_unmap_single(dma_addr_t addr, size_t len,
> + enum dma_data_direction dir)
> +{
> + len = ALIGN(len, ARCH_DMA_MINALIGN);
> + if (dir != DMA_TO_DEVICE)
> + invalidate_dcache_range(addr, addr + len);
> +}
> +
> +static inline void mtk_snor_rmw(struct mtk_snor_priv *priv, u32 reg, u32 set,
> + u32 clr)
> +{
> + u32 val = readl(priv->base + reg);
> +
> + val &= ~clr;
> + val |= set;
> + writel(val, priv->base + reg);
> +}
> +
> +static inline int mtk_snor_cmd_exec(struct mtk_snor_priv *priv, u32 cmd,
> + ulong clk)
> +{
> + unsigned long long delay = CLK_TO_US(priv, clk);
> + u32 reg;
> + int ret;
> +
> + writel(cmd, priv->base + MTK_NOR_REG_CMD);
> +
> + delay = (delay + 1) * 200;
> + ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
> + delay);
> + if (ret < 0)
> + dev_err(priv->dev, "command %u timeout.\n", cmd);
> + return ret;
> +}
> +
> +static void mtk_snor_set_addr(struct mtk_snor_priv *priv,
> + const struct spi_mem_op *op)
> +{
> + u32 addr = op->addr.val;
> + int i;
> +
> + for (i = 0; i < 3; i++) {
> + writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
> + addr >>= 8;
> + }
> + if (op->addr.nbytes == 4) {
> + writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
> + mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
> + } else {
> + mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
> + }
> +}
> +
> +static bool mtk_snor_match_read(const struct spi_mem_op *op)
> +{
> + int dummy = 0;
> +
> + if (op->dummy.buswidth)
> + dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
> +
> + if (op->data.buswidth == 2 || op->data.buswidth == 4) {
> + if (op->addr.buswidth == 1)
> + return dummy == 8;
> + else if (op->addr.buswidth == 2)
> + return dummy == 4;
> + else if (op->addr.buswidth == 4)
> + return dummy == 6;
> + } else if ((op->addr.buswidth == 0) && (op->data.buswidth == 1)) {
> + return dummy == 0;
> + } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
> + if (op->cmd.opcode == 0x03)
> + return dummy == 0;
> + else if (op->cmd.opcode == 0x0b)
> + return dummy == 8;
> + }
> + return false;
> +}
This looks like flash command handling on the SPI side. Can you try to
handle this driver at mtd/spi side as UCLASS_SPI_FLASH?
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller
2020-12-07 17:48 ` Jagan Teki
@ 2021-01-18 4:19 ` SkyLake Huang
0 siblings, 0 replies; 7+ messages in thread
From: SkyLake Huang @ 2021-01-18 4:19 UTC (permalink / raw
To: u-boot
On Tue, 2020-12-08 at 01:48 +0800, Jagan Teki wrote:
> On Fri, Nov 13, 2020 at 8:32 AM SkyLake Huang
> <SkyLake.Huang@mediatek.com> wrote:
> >
> > From: "SkyLake.Huang" <skylake.huang@mediatek.com>
> >
> > This patch adds support for MTK SPI NOR controller, which you
> > can see on mt7622 & mt7629.
> >
> > This controller is designed only for SPI NOR. We can't adjust
> > its bus clock dynamically. Set clock in dts instead.
> >
> > Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
> > ---
> > drivers/spi/Kconfig | 7 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/mtk_snor.c | 597 +++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 605 insertions(+)
> > create mode 100644 drivers/spi/mtk_snor.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index fae2040af8..670af450c1 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -174,6 +174,13 @@ config MT7621_SPI
> > the SPI NOR flash on platforms embedding this Ralink / MediaTek
> > SPI core, like MT7621/7628/7688.
> >
> > +config MTK_SNOR
> > + bool "Mediatek SPI-NOR controller driver"
> > + depends on SPI_MEM
> > + help
> > + Enable the Mediatek SPINOR controller driver. This driver has
> > + better read/write performance with NOR.
> > +
> > config MTK_SNFI_SPI
> > bool "Mediatek SPI memory controller driver"
> > depends on SPI_MEM
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index ae4f2958f8..efe92f6b18 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -38,6 +38,7 @@ obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> > obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> > obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
> > +obj-$(CONFIG_MTK_SNOR) += mtk_snor.o
> > obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
> > obj-$(CONFIG_MSCC_BB_SPI) += mscc_bb_spi.o
> > obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
> > diff --git a/drivers/spi/mtk_snor.c b/drivers/spi/mtk_snor.c
> > new file mode 100644
> > index 0000000000..0a92f1c5a8
> > --- /dev/null
> > +++ b/drivers/spi/mtk_snor.c
> > @@ -0,0 +1,597 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Mediatek SPI-NOR controller driver
> > +//
> > +// Copyright (C) 2020 SkyLake Huang <SkyLake.Huang@mediatek.com>
> > +//
> > +// Some parts are based on drivers/spi/spi-mtk-nor.c of linux version
> > +
> > +#include <common.h>
> > +#include <clk.h>
> > +#include <cpu_func.h>
> > +#include <dm.h>
> > +#include <errno.h>
> > +#include <spi.h>
> > +#include <spi-mem.h>
> > +#include <stdbool.h>
> > +#include <watchdog.h>
> > +#include <dm/pinctrl.h>
> > +#include <dm/device.h>
> > +#include <asm/dma-mapping.h>
> > +#include <linux/dma-direction.h>
> > +#include <linux/completion.h>
> > +#include <linux/bitops.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +
> > +#define DRIVER_NAME "mtk-spi-nor"
> > +
> > +#define MTK_NOR_REG_CMD 0x00
> > +#define MTK_NOR_CMD_WRSR BIT(5)
> > +#define MTK_NOR_CMD_WRITE BIT(4)
> > +#define MTK_NOR_CMD_PROGRAM BIT(2)
> > +#define MTK_NOR_CMD_RDSR BIT(1)
> > +#define MTK_NOR_CMD_READ BIT(0)
> > +#define MTK_NOR_CMD_MASK GENMASK(5, 0)
> > +
> > +#define MTK_NOR_REG_PRG_CNT 0x04
> > +#define MTK_NOR_REG_RDSR 0x08
> > +#define MTK_NOR_REG_RDATA 0x0c
> > +
> > +#define MTK_NOR_REG_RADR0 0x10
> > +#define MTK_NOR_REG_RADR(n) (MTK_NOR_REG_RADR0 + 4 * (n))
> > +#define MTK_NOR_REG_RADR3 0xc8
> > +
> > +#define MTK_NOR_REG_WDATA 0x1c
> > +
> > +#define MTK_NOR_REG_PRGDATA0 0x20
> > +#define MTK_NOR_REG_PRGDATA(n) (MTK_NOR_REG_PRGDATA0 + 4 * (n))
> > +#define MTK_NOR_REG_PRGDATA_MAX 5
> > +
> > +#define MTK_NOR_REG_SHIFT0 0x38
> > +#define MTK_NOR_REG_SHIFT(n) (MTK_NOR_REG_SHIFT0 + 4 * (n))
> > +#define MTK_NOR_REG_SHIFT_MAX 9
> > +
> > +#define MTK_NOR_REG_CFG1 0x60
> > +#define MTK_NOR_FAST_READ BIT(0)
> > +
> > +#define MTK_NOR_REG_CFG2 0x64
> > +#define MTK_NOR_WR_CUSTOM_OP_EN BIT(4)
> > +#define MTK_NOR_WR_BUF_EN BIT(0)
> > +
> > +#define MTK_NOR_REG_PP_DATA 0x98
> > +
> > +#define MTK_NOR_REG_IRQ_STAT 0xa8
> > +#define MTK_NOR_REG_IRQ_EN 0xac
> > +#define MTK_NOR_IRQ_DMA BIT(7)
> > +#define MTK_NOR_IRQ_WRSR BIT(5)
> > +#define MTK_NOR_IRQ_MASK GENMASK(7, 0)
> > +
> > +#define MTK_NOR_REG_CFG3 0xb4
> > +#define MTK_NOR_DISABLE_WREN BIT(7)
> > +#define MTK_NOR_DISABLE_SR_POLL BIT(5)
> > +
> > +#define MTK_NOR_REG_WP 0xc4
> > +#define MTK_NOR_ENABLE_SF_CMD 0x30
> > +
> > +#define MTK_NOR_REG_BUSCFG 0xcc
> > +#define MTK_NOR_4B_ADDR BIT(4)
> > +#define MTK_NOR_QUAD_ADDR BIT(3)
> > +#define MTK_NOR_QUAD_READ BIT(2)
> > +#define MTK_NOR_DUAL_ADDR BIT(1)
> > +#define MTK_NOR_DUAL_READ BIT(0)
> > +#define MTK_NOR_BUS_MODE_MASK GENMASK(4, 0)
> > +
> > +#define MTK_NOR_REG_DMA_CTL 0x718
> > +#define MTK_NOR_DMA_START BIT(0)
> > +
> > +#define MTK_NOR_REG_DMA_FADR 0x71c
> > +#define MTK_NOR_REG_DMA_DADR 0x720
> > +#define MTK_NOR_REG_DMA_END_DADR 0x724
> > +
> > +#define MTK_NOR_PRG_MAX_SIZE 6
> > +// Reading DMA src/dst addresses have to be 16-byte aligned
> > +#define MTK_NOR_DMA_ALIGN 16
> > +#define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
> > +// and we allocate a bounce buffer if destination address isn't aligned.
> > +#define MTK_NOR_BOUNCE_BUF_SIZE PAGE_SIZE
> > +
> > +// Buffered page program can do one 128-byte transfer
> > +#define MTK_NOR_PP_SIZE 128
> > +
> > +#define CLK_TO_US(priv, clkcnt) ((clkcnt) * (1000000) / ((priv)->spi_freq))
> > +
> > +#define MTK_NOR_UNLOCK_ALL 0x0
> > +
> > +struct mtk_snor_priv {
> > + struct device *dev;
> > + void __iomem *base;
> > + u8 *buffer;
> > + struct clk spi_clk;
> > + struct clk ctlr_clk;
> > + unsigned int spi_freq;
> > + bool wbuf_en;
> > +};
> > +
> > +static inline dma_addr_t __dma_map_single(void *vaddr, size_t len,
> > + enum dma_data_direction dir)
> > +{
> > + unsigned long addr = (unsigned long)vaddr;
> > +
> > + len = ALIGN(len, ARCH_DMA_MINALIGN);
> > + if (dir == DMA_FROM_DEVICE)
> > + invalidate_dcache_range(addr, addr + len);
> > + else
> > + flush_dcache_range(addr, addr + len);
> > +
> > + return addr;
> > +}
> > +
> > +static inline void __dma_unmap_single(dma_addr_t addr, size_t len,
> > + enum dma_data_direction dir)
> > +{
> > + len = ALIGN(len, ARCH_DMA_MINALIGN);
> > + if (dir != DMA_TO_DEVICE)
> > + invalidate_dcache_range(addr, addr + len);
> > +}
> > +
> > +static inline void mtk_snor_rmw(struct mtk_snor_priv *priv, u32 reg, u32 set,
> > + u32 clr)
> > +{
> > + u32 val = readl(priv->base + reg);
> > +
> > + val &= ~clr;
> > + val |= set;
> > + writel(val, priv->base + reg);
> > +}
> > +
> > +static inline int mtk_snor_cmd_exec(struct mtk_snor_priv *priv, u32 cmd,
> > + ulong clk)
> > +{
> > + unsigned long long delay = CLK_TO_US(priv, clk);
> > + u32 reg;
> > + int ret;
> > +
> > + writel(cmd, priv->base + MTK_NOR_REG_CMD);
> > +
> > + delay = (delay + 1) * 200;
> > + ret = readl_poll_timeout(priv->base + MTK_NOR_REG_CMD, reg, !(reg & cmd),
> > + delay);
> > + if (ret < 0)
> > + dev_err(priv->dev, "command %u timeout.\n", cmd);
> > + return ret;
> > +}
> > +
> > +static void mtk_snor_set_addr(struct mtk_snor_priv *priv,
> > + const struct spi_mem_op *op)
> > +{
> > + u32 addr = op->addr.val;
> > + int i;
> > +
> > + for (i = 0; i < 3; i++) {
> > + writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR(i));
> > + addr >>= 8;
> > + }
> > + if (op->addr.nbytes == 4) {
> > + writeb(addr & 0xff, priv->base + MTK_NOR_REG_RADR3);
> > + mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, MTK_NOR_4B_ADDR, 0);
> > + } else {
> > + mtk_snor_rmw(priv, MTK_NOR_REG_BUSCFG, 0, MTK_NOR_4B_ADDR);
> > + }
> > +}
> > +
> > +static bool mtk_snor_match_read(const struct spi_mem_op *op)
> > +{
> > + int dummy = 0;
> > +
> > + if (op->dummy.buswidth)
> > + dummy = op->dummy.nbytes * BITS_PER_BYTE / op->dummy.buswidth;
> > +
> > + if (op->data.buswidth == 2 || op->data.buswidth == 4) {
> > + if (op->addr.buswidth == 1)
> > + return dummy == 8;
> > + else if (op->addr.buswidth == 2)
> > + return dummy == 4;
> > + else if (op->addr.buswidth == 4)
> > + return dummy == 6;
> > + } else if ((op->addr.buswidth == 0) && (op->data.buswidth == 1)) {
> > + return dummy == 0;
> > + } else if ((op->addr.buswidth == 1) && (op->data.buswidth == 1)) {
> > + if (op->cmd.opcode == 0x03)
> > + return dummy == 0;
> > + else if (op->cmd.opcode == 0x0b)
> > + return dummy == 8;
> > + }
> > + return false;
> > +}
>
> This looks like flash command handling on the SPI side. Can you try to
> handle this driver at mtd/spi side as UCLASS_SPI_FLASH?
This just double reconfirms whether SPI command is supported by this
controller or not. But since the commands issued by mtd/spi layer works
fine on this controller (at least single-mode looks good), I think I can
remove this function(mtk_snor_match_read). I'll send a v2 patch to
correct this.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 0/2] *** Add support for Mediatek mt762x SoC ***
@ 2021-01-20 7:31 SkyLake Huang
0 siblings, 0 replies; 7+ messages in thread
From: SkyLake Huang @ 2021-01-20 7:31 UTC (permalink / raw
To: u-boot
From: "SkyLake.Huang" <skylake.huang@mediatek.com>
This patch adds support MTK's SPI NOR controller on
mt7622 & mt7629. With this controller, you can access
SPI NOR with better performance on mt762x platform.
SkyLake.Huang (2):
spi: mtk_snor: add support for MTK SPI NOR controller
arm: dts: enable MTK SPI NOR controller driver
arch/arm/dts/mt7622-rfb.dts | 16 +-
arch/arm/dts/mt7622.dtsi | 11 +
arch/arm/dts/mt7629-rfb.dts | 16 +-
arch/arm/dts/mt7629.dtsi | 11 +
configs/mt7622_rfb_defconfig | 3 +-
configs/mt7629_rfb_defconfig | 3 +-
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mtk_snor.c | 563 +++++++++++++++++++++++++++++++++++
9 files changed, 627 insertions(+), 4 deletions(-)
create mode 100644 drivers/spi/mtk_snor.c
--
2.18.0
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2021-01-20 7:31 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-11-13 3:02 [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
2020-11-13 3:02 ` [PATCH 1/2] spi: mtk_snor: add support for MTK SPI NOR controller SkyLake Huang
2020-12-07 17:48 ` Jagan Teki
2021-01-18 4:19 ` SkyLake Huang
2020-11-13 3:02 ` [PATCH 2/2] arm: dts: enable MTK SPI NOR controller driver SkyLake Huang
2020-11-26 3:54 ` [PATCH 0/2] *** Add support for Mediatek mt762x SoC *** SkyLake Huang
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2021-01-20 7:31 SkyLake Huang
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