* [PATCH v1 0/2] Add device nodes for SC7280 SoCs
@ 2021-04-10 2:04 Taniya Das
2021-04-10 2:04 ` [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node Taniya Das
2021-04-10 2:04 ` [PATCH v1 2/2] arm64: dts: qcom: sc7280: Add clock controller nodes Taniya Das
0 siblings, 2 replies; 5+ messages in thread
From: Taniya Das @ 2021-04-10 2:04 UTC (permalink / raw
To: Rob Herring, Bjorn Andersson
Cc: Douglas Anderson, Stephen Boyd, Andy Gross, devicetree,
linux-arm-msm, linux-kernel, Taniya Das
Add device node for cpufreq HW and clock controllers of GPU, DISP, VIDEO, LPASS.
The clock controller nodes are dependent on the following
VIDEO/DISP/GPU: https://lkml.org/lkml/2021/3/16/1624
LPASS: https://lkml.org/lkml/2021/4/9/812
Taniya Das (2):
arm64: dts: qcom: sc7280: Add cpufreq hw node
arm64: dts: qcom: sc7280: Add clock controller nodes
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78 ++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node
2021-04-10 2:04 [PATCH v1 0/2] Add device nodes for SC7280 SoCs Taniya Das
@ 2021-04-10 2:04 ` Taniya Das
2021-04-10 2:13 ` Stephen Boyd
2021-04-20 21:34 ` Matthias Kaehlcke
2021-04-10 2:04 ` [PATCH v1 2/2] arm64: dts: qcom: sc7280: Add clock controller nodes Taniya Das
1 sibling, 2 replies; 5+ messages in thread
From: Taniya Das @ 2021-04-10 2:04 UTC (permalink / raw
To: Rob Herring, Bjorn Andersson
Cc: Douglas Anderson, Stephen Boyd, Andy Gross, devicetree,
linux-arm-msm, linux-kernel, Taniya Das
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2cc4785..cda3f2a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -70,6 +70,7 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -88,6 +89,7 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -103,6 +105,7 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +121,7 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +137,7 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -148,6 +153,7 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -163,6 +169,7 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -178,6 +185,7 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -1116,6 +1124,17 @@
#clock-cells = <1>;
};
};
+
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #freq-domain-cells = <1>;
+ };
};
timer {
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v1 2/2] arm64: dts: qcom: sc7280: Add clock controller nodes
2021-04-10 2:04 [PATCH v1 0/2] Add device nodes for SC7280 SoCs Taniya Das
2021-04-10 2:04 ` [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node Taniya Das
@ 2021-04-10 2:04 ` Taniya Das
1 sibling, 0 replies; 5+ messages in thread
From: Taniya Das @ 2021-04-10 2:04 UTC (permalink / raw
To: Rob Herring, Bjorn Andersson
Cc: Douglas Anderson, Stephen Boyd, Andy Gross, devicetree,
linux-arm-msm, linux-kernel, Taniya Das
Add support for the video, gpu, display, lpass clock controller
device nodes for SC7280 SoC.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 58 ++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index cda3f2a..b59ffff 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -5,8 +5,12 @@
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpass-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -324,6 +328,31 @@
};
};
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+ <0 0x03c04000 0 0x4>,
+ <0 0x03389000 0 0x24>;
+ reg-names = "qdsp6ss", "top_cc", "cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc7280-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
@@ -820,6 +849,35 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sc7280-videocc";
+ reg = <0 0xaaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sc7280-dispcc";
+ reg = <0 0xaf00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node
2021-04-10 2:04 ` [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node Taniya Das
@ 2021-04-10 2:13 ` Stephen Boyd
2021-04-20 21:34 ` Matthias Kaehlcke
1 sibling, 0 replies; 5+ messages in thread
From: Stephen Boyd @ 2021-04-10 2:13 UTC (permalink / raw
To: Bjorn Andersson, Rob Herring, Taniya Das
Cc: Douglas Anderson, Andy Gross, devicetree, linux-arm-msm,
linux-kernel, Taniya Das
Quoting Taniya Das (2021-04-09 19:04:39)
> @@ -1116,6 +1124,17 @@
> #clock-cells = <1>;
> };
> };
> +
> + cpufreq_hw: cpufreq@18591000 {
> + compatible = "qcom,cpufreq-epss";
> + reg = <0 0x18591000 0 0x1000>,
> + <0 0x18592000 0 0x1000>,
> + <0 0x18593000 0 0x1000>;
> + reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
The reg-names provides practically no value. Can you drop it?
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
> + clock-names = "xo", "alternate";
> + #freq-domain-cells = <1>;
> + };
> };
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node
2021-04-10 2:04 ` [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node Taniya Das
2021-04-10 2:13 ` Stephen Boyd
@ 2021-04-20 21:34 ` Matthias Kaehlcke
1 sibling, 0 replies; 5+ messages in thread
From: Matthias Kaehlcke @ 2021-04-20 21:34 UTC (permalink / raw
To: Taniya Das
Cc: Rob Herring, Bjorn Andersson, Douglas Anderson, Stephen Boyd,
Andy Gross, devicetree, linux-arm-msm, linux-kernel
On Sat, Apr 10, 2021 at 07:34:39AM +0530, Taniya Das wrote:
> Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
> cores on SC7280 SoCs.
>
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-04-20 21:34 UTC | newest]
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2021-04-10 2:04 [PATCH v1 0/2] Add device nodes for SC7280 SoCs Taniya Das
2021-04-10 2:04 ` [PATCH v1 1/2] arm64: dts: qcom: sc7280: Add cpufreq hw node Taniya Das
2021-04-10 2:13 ` Stephen Boyd
2021-04-20 21:34 ` Matthias Kaehlcke
2021-04-10 2:04 ` [PATCH v1 2/2] arm64: dts: qcom: sc7280: Add clock controller nodes Taniya Das
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