* [PATCH] clk: analogbits: Fix kernel-doc
@ 2021-06-01 9:44 Yang Li
0 siblings, 0 replies; only message in thread
From: Yang Li @ 2021-06-01 9:44 UTC (permalink / raw
To: paul.walmsley
Cc: mturquette, sboyd, nathan, ndesaulniers, linux-clk, linux-kernel,
clang-built-linux, Yang Li
Fix function name in wrpll-cln28hpc.c kernel-doc comment
to remove a warning found by clang(make W=1 LLVM=1).
drivers/clk/analogbits/wrpll-cln28hpc.c:227: warning: expecting
prototype for wrpll_configure(). Prototype was for
wrpll_configure_for_rate() instead.
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
---
drivers/clk/analogbits/wrpll-cln28hpc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/analogbits/wrpll-cln28hpc.c b/drivers/clk/analogbits/wrpll-cln28hpc.c
index 776ead3..3b19475 100644
--- a/drivers/clk/analogbits/wrpll-cln28hpc.c
+++ b/drivers/clk/analogbits/wrpll-cln28hpc.c
@@ -198,7 +198,7 @@ static int __wrpll_update_parent_rate(struct wrpll_cfg *c,
}
/**
- * wrpll_configure() - compute PLL configuration for a target rate
+ * wrpll_configure_for_rate() - compute PLL configuration for a target rate
* @c: ptr to a struct wrpll_cfg record to write into
* @target_rate: target PLL output clock rate (post-Q-divider)
* @parent_rate: PLL input refclk rate (pre-R-divider)
--
1.8.3.1
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