From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan.Cameron@huawei.com, vishal.l.verma@intel.com,
alison.schofield@intel.com
Subject: [PATCH v3 2/6] cxl/core: Improve CXL core kernel docs
Date: Fri, 30 Jul 2021 13:07:06 -0700 [thread overview]
Message-ID: <162767562636.3322476.12211722876145119343.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <162767561501.3322476.716972045397140827.stgit@dwillia2-desk3.amr.corp.intel.com>
From: Ben Widawsky <ben.widawsky@intel.com>
Now that CXL core's role is well understood, the documentation should
reflect that information.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/core/bus.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c
index 6ce04e3976d2..647b8a00ab36 100644
--- a/drivers/cxl/core/bus.c
+++ b/drivers/cxl/core/bus.c
@@ -12,8 +12,15 @@
/**
* DOC: cxl core
*
- * The CXL core provides a sysfs hierarchy for control devices and a rendezvous
- * point for cross-device interleave coordination through cxl ports.
+ * The CXL core provides a set of interfaces that can be consumed by CXL aware
+ * drivers. The interfaces allow for creation, modification, and destruction of
+ * regions, memory devices, ports, and decoders. CXL aware drivers must register
+ * with the CXL core via these interfaces in order to be able to participate in
+ * cross-device interleave coordination. The CXL core also establishes and
+ * maintains the bridge to the nvdimm subsystem.
+ *
+ * CXL core introduces sysfs hierarchy to control the devices that are
+ * instantiated by the core.
*/
static DEFINE_IDA(cxl_port_ida);
next prev parent reply other threads:[~2021-07-30 20:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-30 20:06 [PATCH v3 0/6] CXL core reorganization Dan Williams
2021-07-30 20:07 ` [PATCH v3 1/6] cxl: Move cxl_core to new directory Dan Williams
2021-07-31 16:35 ` [PATCH v4 " Dan Williams
2021-07-30 20:07 ` Dan Williams [this message]
2021-07-30 20:07 ` [PATCH v3 3/6] cxl/core: Move pmem functionality Dan Williams
2021-07-30 20:07 ` [PATCH v3 4/6] cxl/core: Move register mapping infrastructure Dan Williams
2021-07-30 20:07 ` [PATCH v3 5/6] cxl/pci: Introduce cdevm_file_operations Dan Williams
2021-08-02 15:04 ` Jonathan Cameron
2021-08-02 16:15 ` Dan Williams
2021-08-02 16:30 ` Jonathan Cameron
2021-07-30 20:07 ` [PATCH v3 6/6] cxl/core: Move memdev management to core Dan Williams
2021-08-02 15:13 ` [PATCH v3 0/6] CXL core reorganization Jonathan Cameron
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