From: Satya Priya <quic_c_skakit@quicinc.com>
To: Rob Herring <robh@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Douglas Anderson <dianders@chromium.org>,
Stephen Boyd <swboyd@chromium.org>,
Andy Gross <agross@kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Satya Priya <quic_c_skakit@quicinc.com>,
Taniya Das <quic_tdas@quicinc.com>
Subject: [PATCH V7 1/5] dt-bindings: clock: Add "qcom,adsp-pil-mode" property
Date: Wed, 27 Jul 2022 13:57:53 +0530 [thread overview]
Message-ID: <1658910477-6494-2-git-send-email-quic_c_skakit@quicinc.com> (raw)
In-Reply-To: <1658910477-6494-1-git-send-email-quic_c_skakit@quicinc.com>
The LPASS Peripheral loader clocks would be used to bring
LPASS out of reset, when this property is present.
This is a cleanup done to handle overlap of regmap of
lpasscc and lpass_aon blocks. As a part of this, remove
the "cc" regmap from lpasscc node.
Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml | 6 ++----
.../devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml | 7 +++++++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
index 47028d7..633887d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -36,13 +36,11 @@ properties:
items:
- description: LPASS qdsp6ss register
- description: LPASS top-cc register
- - description: LPASS cc register
reg-names:
items:
- const: qdsp6ss
- const: top_cc
- - const: cc
required:
- compatible
@@ -59,8 +57,8 @@ examples:
#include <dt-bindings/clock/qcom,lpass-sc7280.h>
clock-controller@3000000 {
compatible = "qcom,sc7280-lpasscc";
- reg = <0x03000000 0x40>, <0x03c04000 0x4>, <0x03389000 0x24>;
- reg-names = "qdsp6ss", "top_cc", "cc";
+ reg = <0x03000000 0x40>, <0x03c04000 0x4>;
+ reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
index bad9135..5ccfb24 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
@@ -41,6 +41,12 @@ properties:
reg:
maxItems: 1
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -165,6 +171,7 @@ examples:
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&lpasscore LPASS_CORE_CC_CORE_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao","iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
--
2.7.4
next prev parent reply other threads:[~2022-07-27 8:28 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 8:27 [PATCH V7 0/5] Add support for audio clock gating resets for SC7280 Satya Priya
2022-07-27 8:27 ` Satya Priya [this message]
2022-08-09 21:19 ` [PATCH V7 1/5] dt-bindings: clock: Add "qcom,adsp-pil-mode" property Bjorn Andersson
2022-08-11 10:43 ` Satya Priya Kakitapalli (Temp)
2022-07-27 8:27 ` [PATCH V7 2/5] clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon Satya Priya
2022-07-27 8:27 ` [PATCH V7 3/5] dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280 Satya Priya
2022-07-27 8:27 ` [PATCH V7 4/5] dt-bindings: clock: Add support for external MCLKs for LPASS on SC7280 Satya Priya
2022-07-27 8:27 ` [PATCH V7 5/5] clk: qcom: lpass: Add support for resets & external mclk for SC7280 Satya Priya
2022-08-09 17:19 ` Stephen Boyd
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