From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3407C04A68 for ; Sat, 30 Jul 2022 09:18:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233849AbiG3JSO (ORCPT ); Sat, 30 Jul 2022 05:18:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232154AbiG3JSM (ORCPT ); Sat, 30 Jul 2022 05:18:12 -0400 Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A714F40BD5; Sat, 30 Jul 2022 02:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172690; x=1690708690; h=from:to:cc:subject:date:message-id:mime-version; bh=9DS4bJLebw1lBvzzjml/GDCUoVQ6Slpznv0XDbK9ev4=; b=YlxCfbAXSbgg/M7bAPTE7Hxu+MnMRHSbVXN/DDYs6BPT1lV3CoF8Hlzv FSKlcCGjsWaUa3vyeMbklLAEO2eXDV1W65Z/SjYg62WJBthEUekjn3m71 JiC3XI5wBaGZTmeWuilMM+d8IwhlCFpQlyrodpFL/G9nug0B+4Qq8g/8o U=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 30 Jul 2022 02:18:10 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:09 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:09 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:03 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" CC: Douglas Anderson , Akhil P Oommen , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Philipp Zabel , "Rob Herring" , Stephen Boyd , , , Subject: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface Date: Sat, 30 Jul 2022 14:47:39 +0530 Message-ID: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some clients like adreno gpu driver would like to ensure that its gdsc is collapsed at hardware during a gpu reset sequence. This is because it has a votable gdsc which could be ON due to a vote from another subsystem like tz, hyp etc or due to an internal hardware signal. To allow this, gpucc driver can expose an interface to the client driver using reset framework. Using this the client driver can trigger a polling within the gdsc driver. This series is rebased on top of linus's master branch. Related discussion: https://patchwork.freedesktop.org/patch/493144/ Akhil P Oommen (5): dt-bindings: clk: qcom: Support gpu cx gdsc reset clk: qcom: Allow custom reset ops clk: qcom: gpucc-sc7280: Add cx collapse reset support clk: qcom: gdsc: Add a reset op to poll gdsc collapse arm64: dts: qcom: sc7280: Add Reset support for gpu arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++ drivers/clk/qcom/reset.c | 6 ++++++ drivers/clk/qcom/reset.h | 2 ++ include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 7 files changed, 46 insertions(+), 4 deletions(-) -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0F09CC04A68 for ; Sat, 30 Jul 2022 09:18:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1793A10F36C; Sat, 30 Jul 2022 09:18:12 +0000 (UTC) Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id E029110F36C; Sat, 30 Jul 2022 09:18:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1659172691; x=1690708691; h=from:to:cc:subject:date:message-id:mime-version; bh=9DS4bJLebw1lBvzzjml/GDCUoVQ6Slpznv0XDbK9ev4=; b=BfJ9qiKmAgQdJkQ+QDwK8zsaJVe3w580UGN2zk5yZqkHo4iBHMTYzzI6 09WT3tsIfWZr9sLo4dgIc21XS+BJdkjqo88s2yaOHN2xlxAZmwvZadoV2 aU7kjxeF9kwABRdyppXAhdcm772aaFY+/c1WWHE8iEEJJUQW5NLU5qNmK 0=; Received: from ironmsg07-lv.qualcomm.com ([10.47.202.151]) by alexa-out.qualcomm.com with ESMTP; 30 Jul 2022 02:18:10 -0700 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg07-lv.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2022 02:18:09 -0700 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:09 -0700 Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Sat, 30 Jul 2022 02:18:03 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" Subject: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface Date: Sat, 30 Jul 2022 14:47:39 +0530 Message-ID: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Akhil P Oommen , Michael Turquette , Konrad Dybcio , Douglas Anderson , Rob Herring , linux-kernel@vger.kernel.org, Stephen Boyd , Andy Gross , Krzysztof Kozlowski , linux-clk@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some clients like adreno gpu driver would like to ensure that its gdsc is collapsed at hardware during a gpu reset sequence. This is because it has a votable gdsc which could be ON due to a vote from another subsystem like tz, hyp etc or due to an internal hardware signal. To allow this, gpucc driver can expose an interface to the client driver using reset framework. Using this the client driver can trigger a polling within the gdsc driver. This series is rebased on top of linus's master branch. Related discussion: https://patchwork.freedesktop.org/patch/493144/ Akhil P Oommen (5): dt-bindings: clk: qcom: Support gpu cx gdsc reset clk: qcom: Allow custom reset ops clk: qcom: gpucc-sc7280: Add cx collapse reset support clk: qcom: gdsc: Add a reset op to poll gdsc collapse arm64: dts: qcom: sc7280: Add Reset support for gpu arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- drivers/clk/qcom/gdsc.h | 7 +++++++ drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++ drivers/clk/qcom/reset.c | 6 ++++++ drivers/clk/qcom/reset.h | 2 ++ include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ 7 files changed, 46 insertions(+), 4 deletions(-) -- 2.7.4