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Shutemov" , "H. Peter Anvin" , Michael Roth , Joerg Roedel , Andy Lutomirski , Peter Zijlstra References: <20220614120231.48165-1-kirill.shutemov@linux.intel.com> <658c455c40e8950cb046dd885dd19dc1c52d060a.1659103274.git.thomas.lendacky@amd.com> <9da5204f-5c8f-b47b-bcc6-d68ca63db08d@amd.com> <377f6c30-bdfc-55a4-bda7-f29c60c53300@intel.com> <70a5c939-16a6-d5e0-2e38-ac7adbed5fc1@intel.com> From: Tom Lendacky In-Reply-To: <70a5c939-16a6-d5e0-2e38-ac7adbed5fc1@intel.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DM6PR11CA0060.namprd11.prod.outlook.com (2603:10b6:5:14c::37) To DM4PR12MB5229.namprd12.prod.outlook.com (2603:10b6:5:398::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e13aa24a-bcd3-4057-18ec-08da719e9b44 X-MS-TrafficTypeDiagnostic: MWHPR12MB1629:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Trhi5mPLSpqqudw9sTe+fs6gmrqwKHNbUuuCB6UAaTFwbCEcs1bOQOZiDKYZjgqdcUEZVuCyZE0mkEiK9xm6UGKmU4ir3Z/Kwitxtqar3cDWUAiezQ03GT1CxPOOsLYCDi9IepfIwa13wAjR+k9o01pSElhDW+x828EVO6JsVeXQ2j7gY/7mu8InHW3wdy+m2VkX09lNn25xmRdSEoRhTJlP4KM90Rdp4fUbmLvkI6Zj3h32vVSOczQz1wpuNFjUyNlB+JBVvuFbMia3Q4I5ECU/0horzV4VZtaRn7FrlnDL+i0DaTTMzx1JhsvGQ7rDF/qsPMfTBEqEr0zkOTonUUSQBZwjNwqE8sMMJswBEvOhb+5kSQ1396BclK6ERTl3qp5FVZgRZsj6qvkyDaafmTMM1VlIDgccozYRYwSxXVKVdkE7SN5/e5p/rHHoVagivf0mP1poKTQmGV6T8uVqq+m08n0ntoWQWQ5HiTH8UtA11dwhUqpSOYN2Ad+iu0kp6DtKc0MIo12WcXtIcNl8SKmDPFTRhVqLDGb+6drjASFV2g5xsQuMNrw1vwojkIMjKJ2GLTG3fN0KpXRFXPXMi/gnXUEjEEmFzOQpFMuLbHzlAYx2XNSptEEl5wba9HFZgp5dHCFkfA21PfomJkNWBLKrV8PiTdPL0GhCtbo1hj7pcH0b4c+FFxWNnNu71T0gIOAb5CEquKwpUPy7m0/bNWQ8vEsTK8LqtO9+skki1eB/3zsHCI01Aj3msyRGvb6rLN07GuY3ahsluA4uAMfZdoiWXZdXgfnvftAhdv6LVvUfkKKZD5Y/xSSdaWdl/ag00OPC+2ESYpuzd+ZPcEP5Pg== X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM4PR12MB5229.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230016)(4636009)(376002)(39860400002)(396003)(366004)(346002)(136003)(2616005)(83380400001)(54906003)(186003)(53546011)(6512007)(36756003)(6506007)(31686004)(41300700001)(26005)(7416002)(2906002)(86362001)(5660300002)(66946007)(8676002)(66556008)(66476007)(316002)(31696002)(478600001)(6486002)(8936002)(38100700002)(4326008)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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How frequent are they? Are they performance sensitive? > That'll help us decide if the design here is appropriate or not. Without submitting a v2, here's what the updated paragraph would look like: Page state changes occur whenever DMA memory is allocated or memory needs to be shared with the hypervisor (kvmclock, attestation reports, etc.). A per-CPU structure is chosen over a single PSC structure protected with a lock because these changes can be initiated from interrupt or soft-interrupt context (e.g. the NVMe driver). Protect the use of the per-CPU structure by disabling interrupts during page state changes. Since the set_pages_state() path is the only path into vmgexit_psc(), rename vmgexit_psc() to __vmgexit_psc() and remove the calls to disable interrupts which are now performed by set_pages_state(). Hopefully there aren't a lot of page state changes occurring once a system has booted, so maybe a static struct with a lock would work. I am a bit worried about an NMI occurring during a page state change that requires a lock. I suppose, in_nmi() can be used to detect that and go the MSR protocol route to avoid a deadlock. I can investigate that if the 2K-extra per-CPU is not desired. Thanks, Tom