From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 07/15] drm/i915: gen specific ring init Date: Tue, 17 Dec 2013 09:52:51 +0100 Message-ID: <20131217085250.GM9804@phenom.ffwll.local> References: <1387255851-24824-1-git-send-email-benjamin.widawsky@intel.com> <1387255851-24824-8-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by gabe.freedesktop.org (Postfix) with ESMTP id 875F0FA1D0 for ; Tue, 17 Dec 2013 00:51:59 -0800 (PST) Received: by mail-ea0-f172.google.com with SMTP id q10so2302646ead.17 for ; Tue, 17 Dec 2013 00:51:58 -0800 (PST) Content-Disposition: inline In-Reply-To: <1387255851-24824-8-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Mon, Dec 16, 2013 at 08:50:43PM -0800, Ben Widawsky wrote: > Gen8 has already had some differentiation with how it handles rings. > Semaphores bring yet more differences, and now is as good a time as any > to do the split. > > Also, since gen8 doesn't actually use semaphores up until this point, > put the proper "NULL" values in for the mbox info. > > v2: v1 had a stale commit message > > Signed-off-by: Ben Widawsky Subject should probably say "gen_8_ specific ring init" since for the render ring we already have gen specific stuff. I can do this color-adjustment when applying if nothing else pops up ;-) -Daniel > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 134 ++++++++++++++++++++++---------- > 1 file changed, 92 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 7a8c5d8..db63a5c 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1857,19 +1857,33 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > ring->id = RCS; > ring->mmio_base = RENDER_RING_BASE; > > - if (INTEL_INFO(dev)->gen >= 6) { > + if (INTEL_INFO(dev)->gen >= 8) { > + ring->add_request = gen6_add_request; > + ring->flush = gen8_render_ring_flush; > + ring->irq_get = gen8_ring_get_irq; > + ring->irq_put = gen8_ring_put_irq; > + ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; > + ring->get_seqno = gen6_ring_get_seqno; > + ring->set_seqno = ring_set_seqno; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.signal_mbox[RCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > + } else if (INTEL_INFO(dev)->gen >= 6) { > ring->add_request = gen6_add_request; > ring->flush = gen7_render_ring_flush; > if (INTEL_INFO(dev)->gen == 6) > ring->flush = gen6_render_ring_flush; > - if (INTEL_INFO(dev)->gen >= 8) { > - ring->flush = gen8_render_ring_flush; > - ring->irq_get = gen8_ring_get_irq; > - ring->irq_put = gen8_ring_put_irq; > - } else { > - ring->irq_get = gen6_ring_get_irq; > - ring->irq_put = gen6_ring_put_irq; > - } > + ring->irq_get = gen6_ring_get_irq; > + ring->irq_put = gen6_ring_put_irq; > ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; > ring->get_seqno = gen6_ring_get_seqno; > ring->set_seqno = ring_set_seqno; > @@ -1911,6 +1925,7 @@ int intel_init_render_ring_buffer(struct drm_device *dev) > ring->irq_enable_mask = I915_USER_INTERRUPT; > } > ring->write_tail = ring_write_tail; > + > if (IS_HASWELL(dev)) > ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; > else if (IS_GEN8(dev)) > @@ -2044,24 +2059,35 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) > ring->irq_put = gen8_ring_put_irq; > ring->dispatch_execbuffer = > gen8_ring_dispatch_execbuffer; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.signal_mbox[RCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > } else { > ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; > ring->irq_get = gen6_ring_get_irq; > ring->irq_put = gen6_ring_put_irq; > ring->dispatch_execbuffer = > gen6_ring_dispatch_execbuffer; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VR; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VB; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_VVE; > + ring->semaphore.signal_mbox[RCS] = GEN6_RVSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_BVSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_VEVSYNC; > } > - ring->semaphore.sync_to = gen6_ring_sync; > - if (i915_semaphore_is_enabled(dev)) > - ring->semaphore.signal = gen6_signal; > - ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VR; > - ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VB; > - ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_VVE; > - ring->semaphore.signal_mbox[RCS] = GEN6_RVSYNC; > - ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > - ring->semaphore.signal_mbox[BCS] = GEN6_BVSYNC; > - ring->semaphore.signal_mbox[VECS] = GEN6_VEVSYNC; > } else { > ring->mmio_base = BSD_RING_BASE; > ring->flush = bsd_ring_flush; > @@ -2104,23 +2130,35 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) > ring->irq_get = gen8_ring_get_irq; > ring->irq_put = gen8_ring_put_irq; > ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.signal_mbox[RCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > } else { > ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; > ring->irq_get = gen6_ring_get_irq; > ring->irq_put = gen6_ring_put_irq; > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_BR; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_BV; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_BVE; > + ring->semaphore.signal_mbox[RCS] = GEN6_RBSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_VBSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_VEBSYNC; > } > - ring->semaphore.sync_to = gen6_ring_sync; > - if (i915_semaphore_is_enabled(dev)) > - ring->semaphore.signal = gen6_signal; > - ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_BR; > - ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_BV; > - ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_BVE; > - ring->semaphore.signal_mbox[RCS] = GEN6_RBSYNC; > - ring->semaphore.signal_mbox[VCS] = GEN6_VBSYNC; > - ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > - ring->semaphore.signal_mbox[VECS] = GEN6_VEBSYNC; > + > ring->init = init_ring_common; > > return intel_init_ring_buffer(dev, ring); > @@ -2147,23 +2185,35 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) > ring->irq_get = gen8_ring_get_irq; > ring->irq_put = gen8_ring_put_irq; > ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.signal_mbox[RCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_NOSYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > } else { > ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; > ring->irq_get = hsw_vebox_get_irq; > ring->irq_put = hsw_vebox_put_irq; > + ring->semaphore.sync_to = gen6_ring_sync; > + if (i915_semaphore_is_enabled(dev)) > + ring->semaphore.signal = gen6_signal; > + ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VER; > + ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_VEV; > + ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VEB; > + ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > + ring->semaphore.signal_mbox[RCS] = GEN6_RVESYNC; > + ring->semaphore.signal_mbox[VCS] = GEN6_VVESYNC; > + ring->semaphore.signal_mbox[BCS] = GEN6_BVESYNC; > + ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; > } > - ring->semaphore.sync_to = gen6_ring_sync; > - if (i915_semaphore_is_enabled(dev)) > - ring->semaphore.signal = gen6_signal; > - ring->semaphore.mbox[RCS] = MI_SEMAPHORE_SYNC_VER; > - ring->semaphore.mbox[VCS] = MI_SEMAPHORE_SYNC_VEV; > - ring->semaphore.mbox[BCS] = MI_SEMAPHORE_SYNC_VEB; > - ring->semaphore.mbox[VECS] = MI_SEMAPHORE_SYNC_INVALID; > - ring->semaphore.signal_mbox[RCS] = GEN6_RVESYNC; > - ring->semaphore.signal_mbox[VCS] = GEN6_VVESYNC; > - ring->semaphore.signal_mbox[BCS] = GEN6_BVESYNC; > - ring->semaphore.signal_mbox[VECS] = GEN6_NOSYNC; > + > ring->init = init_ring_common; > > return intel_init_ring_buffer(dev, ring); > -- > 1.8.5.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch