* [PATCH 1/3] drm/i915: consider the source max DP lane count too
@ 2014-04-24 21:22 Paulo Zanoni
2014-04-25 7:16 ` Jani Nikula
0 siblings, 1 reply; 11+ messages in thread
From: Paulo Zanoni @ 2014-04-24 21:22 UTC (permalink / raw
To: intel-gfx; +Cc: Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Even if the panel claims it can support 4 lanes, there's the
possibility that the HW can't, so consider this while selecting the
max lane count.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 104998e..19537a6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
return max_link_bw;
}
+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ u8 source_max, sink_max;
+
+ source_max = 4;
+ if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
+ (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
+ source_max = 2;
+
+ sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+
+ return min(source_max, sink_max);
+}
+
/*
* The units on the numbers in the next two are... bizarre. Examples will
* make it clearer; this one parallels an example in the eDP spec.
@@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
}
max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
- max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+ max_lanes = intel_dp_max_lane_count(intel_dp);
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
@@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc *intel_crtc = encoder->new_crtc;
struct intel_connector *intel_connector = intel_dp->attached_connector;
int lane_count, clock;
- int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ int max_lane_count = intel_dp_max_lane_count(intel_dp);
/* Conveniently, the link BW constants become indices with a shift...*/
int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
int bpp, mode_rate;
--
1.9.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: consider the source max DP lane count too
2014-04-24 21:22 Paulo Zanoni
@ 2014-04-25 7:16 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2014-04-25 7:16 UTC (permalink / raw
To: Paulo Zanoni, intel-gfx; +Cc: Paulo Zanoni
On Fri, 25 Apr 2014, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Even if the panel claims it can support 4 lanes, there's the
> possibility that the HW can't, so consider this while selecting the
> max lane count.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 104998e..19537a6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -120,6 +120,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> return max_link_bw;
> }
>
> +static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + u8 source_max, sink_max;
> +
> + source_max = 4;
> + if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
> + (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
> + source_max = 2;
Wow, good catch. Are you aware of similar restrictions on other
platforms?
Does this potentially fix
https://bugs.freedesktop.org/show_bug.cgi?id=73539 ?
BR,
Jani.
> +
> + sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> +
> + return min(source_max, sink_max);
> +}
> +
> /*
> * The units on the numbers in the next two are... bizarre. Examples will
> * make it clearer; this one parallels an example in the eDP spec.
> @@ -170,7 +186,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> }
>
> max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
> - max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
> + max_lanes = intel_dp_max_lane_count(intel_dp);
>
> max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> mode_rate = intel_dp_link_required(target_clock, 18);
> @@ -764,7 +780,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc *intel_crtc = encoder->new_crtc;
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> int lane_count, clock;
> - int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> + int max_lane_count = intel_dp_max_lane_count(intel_dp);
> /* Conveniently, the link BW constants become indices with a shift...*/
> int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
> int bpp, mode_rate;
> --
> 1.9.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 1/3] drm/i915: consider the source max DP lane count too
@ 2014-05-06 11:56 Jani Nikula
2014-05-06 11:56 ` [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding Jani Nikula
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Jani Nikula @ 2014-05-06 11:56 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula, Paulo Zanoni
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Even if the panel claims it can support 4 lanes, there's the
possibility that the HW can't, so consider this while selecting the
max lane count.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 87b0a515d7a5..3dde9076d9d7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -121,6 +121,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
return max_link_bw;
}
+static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
+{
+ struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ u8 source_max, sink_max;
+
+ source_max = 4;
+ if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
+ (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
+ source_max = 2;
+
+ sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
+
+ return min(source_max, sink_max);
+}
+
/*
* The units on the numbers in the next two are... bizarre. Examples will
* make it clearer; this one parallels an example in the eDP spec.
@@ -171,7 +187,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
}
max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
- max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
+ max_lanes = intel_dp_max_lane_count(intel_dp);
max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
mode_rate = intel_dp_link_required(target_clock, 18);
@@ -769,7 +785,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc *intel_crtc = encoder->new_crtc;
struct intel_connector *intel_connector = intel_dp->attached_connector;
int lane_count, clock;
- int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
+ int max_lane_count = intel_dp_max_lane_count(intel_dp);
/* Conveniently, the link BW constants become indices with a shift...*/
int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
int bpp, mode_rate;
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding
2014-05-06 11:56 [PATCH 1/3] drm/i915: consider the source max DP lane count too Jani Nikula
@ 2014-05-06 11:56 ` Jani Nikula
2014-05-06 13:41 ` Damien Lespiau
2014-05-06 11:56 ` [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2014-05-06 11:56 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula, Paulo Zanoni
Use defines, do not set anything if VBT has values unknown to us.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_bios.c | 52 ++++++++++++++++++++++++++++-----------
1 file changed, 38 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 2945f57c53ee..6b6509656f16 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -598,47 +598,71 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
dev_priv->vbt.edp_pps = *edp_pps;
- dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 :
- DP_LINK_BW_1_62;
+ switch (edp_link_params->rate) {
+ case EDP_RATE_1_62:
+ dev_priv->vbt.edp_rate = DP_LINK_BW_1_62;
+ break;
+ case EDP_RATE_2_7:
+ dev_priv->vbt.edp_rate = DP_LINK_BW_2_7;
+ break;
+ default:
+ DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n",
+ edp_link_params->rate);
+ break;
+ }
+
switch (edp_link_params->lanes) {
- case 0:
+ case EDP_LANE_1:
dev_priv->vbt.edp_lanes = 1;
break;
- case 1:
+ case EDP_LANE_2:
dev_priv->vbt.edp_lanes = 2;
break;
- case 3:
- default:
+ case EDP_LANE_4:
dev_priv->vbt.edp_lanes = 4;
break;
+ default:
+ DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n",
+ edp_link_params->lanes);
+ break;
}
+
switch (edp_link_params->preemphasis) {
- case 0:
+ case EDP_PREEMPHASIS_NONE:
dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0;
break;
- case 1:
+ case EDP_PREEMPHASIS_3_5dB:
dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5;
break;
- case 2:
+ case EDP_PREEMPHASIS_6dB:
dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6;
break;
- case 3:
+ case EDP_PREEMPHASIS_9_5dB:
dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5;
break;
+ default:
+ DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n",
+ edp_link_params->preemphasis);
+ break;
}
+
switch (edp_link_params->vswing) {
- case 0:
+ case EDP_VSWING_0_4V:
dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400;
break;
- case 1:
+ case EDP_VSWING_0_6V:
dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600;
break;
- case 2:
+ case EDP_VSWING_0_8V:
dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800;
break;
- case 3:
+ case EDP_VSWING_1_2V:
dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200;
break;
+ default:
+ DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n",
+ edp_link_params->vswing);
+ break;
}
}
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP
2014-05-06 11:56 [PATCH 1/3] drm/i915: consider the source max DP lane count too Jani Nikula
2014-05-06 11:56 ` [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding Jani Nikula
@ 2014-05-06 11:56 ` Jani Nikula
2014-05-06 13:51 ` Damien Lespiau
2014-05-06 12:55 ` [PATCH 1/3] drm/i915: consider the source max DP lane count too Damien Lespiau
2014-05-06 13:34 ` Damien Lespiau
3 siblings, 1 reply; 11+ messages in thread
From: Jani Nikula @ 2014-05-06 11:56 UTC (permalink / raw
To: intel-gfx; +Cc: jani.nikula, Paulo Zanoni
Most likely the minimums for both should be enough for enabling the
native resolution on the eDP, and we'll end up using the predetermined
optimal link config for the panel.
v2: Add debug prints.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73539
Tested-by: Markus Blank-Burian <burian@muenster.de>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 30 +++++++++++++++++++++++-------
1 file changed, 23 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3dde9076d9d7..511d7804335a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -785,8 +785,10 @@ intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc *intel_crtc = encoder->new_crtc;
struct intel_connector *intel_connector = intel_dp->attached_connector;
int lane_count, clock;
+ int min_lane_count = 1;
int max_lane_count = intel_dp_max_lane_count(intel_dp);
/* Conveniently, the link BW constants become indices with a shift...*/
+ int min_clock = 0;
int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
int bpp, mode_rate;
static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
@@ -819,19 +821,33 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
* bpc in between. */
bpp = pipe_config->pipe_bpp;
- if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
- dev_priv->vbt.edp_bpp < bpp) {
- DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
- dev_priv->vbt.edp_bpp);
- bpp = dev_priv->vbt.edp_bpp;
+ if (is_edp(intel_dp)) {
+ if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
+ DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
+ dev_priv->vbt.edp_bpp);
+ bpp = dev_priv->vbt.edp_bpp;
+ }
+
+ if (dev_priv->vbt.edp_lanes) {
+ min_lane_count = min(dev_priv->vbt.edp_lanes,
+ max_lane_count);
+ DRM_DEBUG_KMS("using min %u lanes per VBT\n",
+ min_lane_count);
+ }
+
+ if (dev_priv->vbt.edp_rate) {
+ min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
+ DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
+ bws[min_clock]);
+ }
}
for (; bpp >= 6*3; bpp -= 2*3) {
mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
bpp);
- for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
- for (clock = 0; clock <= max_clock; clock++) {
+ for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
+ for (clock = min_clock; clock <= max_clock; clock++) {
link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
link_avail = intel_dp_max_data_rate(link_clock,
lane_count);
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: consider the source max DP lane count too
2014-05-06 11:56 [PATCH 1/3] drm/i915: consider the source max DP lane count too Jani Nikula
2014-05-06 11:56 ` [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding Jani Nikula
2014-05-06 11:56 ` [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula
@ 2014-05-06 12:55 ` Damien Lespiau
2014-05-06 16:59 ` Jani Nikula
2014-05-06 13:34 ` Damien Lespiau
3 siblings, 1 reply; 11+ messages in thread
From: Damien Lespiau @ 2014-05-06 12:55 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Even if the panel claims it can support 4 lanes, there's the
> possibility that the HW can't, so consider this while selecting the
> max lane count.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 87b0a515d7a5..3dde9076d9d7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -121,6 +121,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
> return max_link_bw;
> }
>
> +static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + u8 source_max, sink_max;
> +
> + source_max = 4;
> + if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
> + (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
> + source_max = 2;
> +
> + sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
> +
> + return min(source_max, sink_max);
> +}
> +
> /*
> * The units on the numbers in the next two are... bizarre. Examples will
> * make it clearer; this one parallels an example in the eDP spec.
> @@ -171,7 +187,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
> }
>
> max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
> - max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
> + max_lanes = intel_dp_max_lane_count(intel_dp);
>
> max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
> mode_rate = intel_dp_link_required(target_clock, 18);
> @@ -769,7 +785,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc *intel_crtc = encoder->new_crtc;
> struct intel_connector *intel_connector = intel_dp->attached_connector;
> int lane_count, clock;
> - int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
> + int max_lane_count = intel_dp_max_lane_count(intel_dp);
> /* Conveniently, the link BW constants become indices with a shift...*/
> int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
> int bpp, mode_rate;
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: consider the source max DP lane count too
2014-05-06 11:56 [PATCH 1/3] drm/i915: consider the source max DP lane count too Jani Nikula
` (2 preceding siblings ...)
2014-05-06 12:55 ` [PATCH 1/3] drm/i915: consider the source max DP lane count too Damien Lespiau
@ 2014-05-06 13:34 ` Damien Lespiau
2014-05-06 13:39 ` Damien Lespiau
3 siblings, 1 reply; 11+ messages in thread
From: Damien Lespiau @ 2014-05-06 13:34 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Even if the panel claims it can support 4 lanes, there's the
> possibility that the HW can't, so consider this while selecting the
> max lane count.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Note that we also have an eDP lane count in the VBT we may want to factor
in here as well.
--
Damien
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: consider the source max DP lane count too
2014-05-06 13:34 ` Damien Lespiau
@ 2014-05-06 13:39 ` Damien Lespiau
0 siblings, 0 replies; 11+ messages in thread
From: Damien Lespiau @ 2014-05-06 13:39 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 06, 2014 at 02:34:41PM +0100, Damien Lespiau wrote:
> On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Even if the panel claims it can support 4 lanes, there's the
> > possibility that the HW can't, so consider this while selecting the
> > max lane count.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Note that we also have an eDP lane count in the VBT we may want to factor
> in here as well.
Ah, that's what this series is all about, discard this comment then.
--
Damien
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding
2014-05-06 11:56 ` [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding Jani Nikula
@ 2014-05-06 13:41 ` Damien Lespiau
0 siblings, 0 replies; 11+ messages in thread
From: Damien Lespiau @ 2014-05-06 13:41 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 06, 2014 at 02:56:51PM +0300, Jani Nikula wrote:
> Use defines, do not set anything if VBT has values unknown to us.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP
2014-05-06 11:56 ` [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula
@ 2014-05-06 13:51 ` Damien Lespiau
0 siblings, 0 replies; 11+ messages in thread
From: Damien Lespiau @ 2014-05-06 13:51 UTC (permalink / raw
To: Jani Nikula; +Cc: intel-gfx, Paulo Zanoni
On Tue, May 06, 2014 at 02:56:52PM +0300, Jani Nikula wrote:
> Most likely the minimums for both should be enough for enabling the
> native resolution on the eDP, and we'll end up using the predetermined
> optimal link config for the panel.
>
> v2: Add debug prints.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73539
> Tested-by: Markus Blank-Burian <burian@muenster.de>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
--
Damien
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915: consider the source max DP lane count too
2014-05-06 12:55 ` [PATCH 1/3] drm/i915: consider the source max DP lane count too Damien Lespiau
@ 2014-05-06 16:59 ` Jani Nikula
0 siblings, 0 replies; 11+ messages in thread
From: Jani Nikula @ 2014-05-06 16:59 UTC (permalink / raw
To: Damien Lespiau; +Cc: intel-gfx, Paulo Zanoni
On Tue, 06 May 2014, Damien Lespiau <damien.lespiau@intel.com> wrote:
> On Tue, May 06, 2014 at 02:56:50PM +0300, Jani Nikula wrote:
>> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>>
>> Even if the panel claims it can support 4 lanes, there's the
>> possibility that the HW can't, so consider this while selecting the
>> max lane count.
>>
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Series pushed to -fixes, thanks for the swift review!
BR,
Jani.
>
> --
> Damien
>
>> ---
>> drivers/gpu/drm/i915/intel_dp.c | 20 ++++++++++++++++++--
>> 1 file changed, 18 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>> index 87b0a515d7a5..3dde9076d9d7 100644
>> --- a/drivers/gpu/drm/i915/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/intel_dp.c
>> @@ -121,6 +121,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp)
>> return max_link_bw;
>> }
>>
>> +static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
>> +{
>> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>> + struct drm_device *dev = intel_dig_port->base.base.dev;
>> + u8 source_max, sink_max;
>> +
>> + source_max = 4;
>> + if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
>> + (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
>> + source_max = 2;
>> +
>> + sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
>> +
>> + return min(source_max, sink_max);
>> +}
>> +
>> /*
>> * The units on the numbers in the next two are... bizarre. Examples will
>> * make it clearer; this one parallels an example in the eDP spec.
>> @@ -171,7 +187,7 @@ intel_dp_mode_valid(struct drm_connector *connector,
>> }
>>
>> max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
>> - max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
>> + max_lanes = intel_dp_max_lane_count(intel_dp);
>>
>> max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
>> mode_rate = intel_dp_link_required(target_clock, 18);
>> @@ -769,7 +785,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>> struct intel_crtc *intel_crtc = encoder->new_crtc;
>> struct intel_connector *intel_connector = intel_dp->attached_connector;
>> int lane_count, clock;
>> - int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
>> + int max_lane_count = intel_dp_max_lane_count(intel_dp);
>> /* Conveniently, the link BW constants become indices with a shift...*/
>> int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
>> int bpp, mode_rate;
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2014-05-06 16:59 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-06 11:56 [PATCH 1/3] drm/i915: consider the source max DP lane count too Jani Nikula
2014-05-06 11:56 ` [PATCH 2/3] drm/i915: clean up VBT eDP link param decoding Jani Nikula
2014-05-06 13:41 ` Damien Lespiau
2014-05-06 11:56 ` [PATCH 3/3] drm/i915: use lane count and link rate from VBT as minimums for eDP Jani Nikula
2014-05-06 13:51 ` Damien Lespiau
2014-05-06 12:55 ` [PATCH 1/3] drm/i915: consider the source max DP lane count too Damien Lespiau
2014-05-06 16:59 ` Jani Nikula
2014-05-06 13:34 ` Damien Lespiau
2014-05-06 13:39 ` Damien Lespiau
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2014-04-24 21:22 Paulo Zanoni
2014-04-25 7:16 ` Jani Nikula
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