From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56658) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5J11-0007sm-V7 for qemu-devel@nongnu.org; Wed, 17 Jun 2015 15:28:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z5J0w-0004KU-Is for qemu-devel@nongnu.org; Wed, 17 Jun 2015 15:28:51 -0400 Received: from mail-qg0-f54.google.com ([209.85.192.54]:36767) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z5J0w-0004K9-Fa for qemu-devel@nongnu.org; Wed, 17 Jun 2015 15:28:46 -0400 Received: by qgal13 with SMTP id l13so18887156qga.3 for ; Wed, 17 Jun 2015 12:28:46 -0700 (PDT) Date: Wed, 17 Jun 2015 15:28:44 -0400 From: Kevin O'Connor Message-ID: <20150617192843.GB27117@morn.localdomain> References: <1434545105-5811-1-git-send-email-lersek@redhat.com> <1434545105-5811-8-git-send-email-lersek@redhat.com> <20150617155237-mutt-send-email-mst@redhat.com> <20150617141820.GA11337@morn.localdomain> <55818819.3010107@redhat.com> <20150617150544.GA26500@redhat.com> <5581B97E.8020707@redhat.com> <20150617204828-mutt-send-email-mst@redhat.com> <5581C74C.5070405@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5581C74C.5070405@redhat.com> Subject: Re: [Qemu-devel] [PATCH v6 7/7] hw/pci-bridge: format SeaBIOS-compliant OFW device node for PXB List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laszlo Ersek , "Michael S. Tsirkin" Cc: Marcel Apfelbaum , Markus Armbruster , qemu-devel@nongnu.org On Wed, Jun 17, 2015 at 09:15:24PM +0200, Laszlo Ersek wrote: > On 06/17/15 20:54, Michael S. Tsirkin wrote: > > Right. But what I was discussing is a different issue. The point is > > that it does not make sense to have /pci@i0cf8 under two hierarchies: > > it's the same register. What happens is that you access /pci@i0cf8 and > > then *through that* you access another pci root. Not the other way > > around. The proposal thus is to switch to /pci@i0cf8/pci-root@N in > > seabios, > > For me this is still Question 1 -- 'everything in that pattern that is > not "N"'. > > You seem to care about the *semantics* of that OFW device path fragment. > I don't. First, the relevant IEEE spec is prohibitively hard for me to > interpret semantically. Second, there is no known firmware that actually > looks at the "i0cf8" unit-address term and decides *based on that term* > that it has to talk PCI via 0xCF8 and 0xCFC. In other words, the current > second node is entirely opaque in my interpretation. > > > unconditionally - not if (QEMU). > > This might qualify as some kind of semantic cleanup, but it will > nonetheless break the SeaBIOS boot options expressed in OFW notation > that are already persistently stored in cbfs, on physical machines. (As > far as I understood.) It might not break the Coreboot-SeaBIOS interface, > but it might invalidate preexistent entries that exist in the prior form > (wherever they exist on physical hardware). > > > And I thought Kevin agreed > > it's a good idea. > > > > Kevin - is this a good summary of your opinion? > > Kevin, please do answer. It is true that it would "invalidate preexistent entries" for coreboot/seabios users that upgrade, but I think that is manageable. So I defer the syntax discussion and decisions to the QEMU developers that are doing the bulk of the work. -Kevin