Re: [PATCH v5 6/6] drm/i915/gen8: Add WaRsRestoreWithPerCtxtBb workaround

From: Chris Wilson <chris@chris-wilson.co.uk>
To: Arun Siluvery <arun.siluvery@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v5 6/6] drm/i915/gen8: Add WaRsRestoreWithPerCtxtBb workaround
Date: Fri, 19 Jun 2015 10:35:58 +0100	[thread overview]
Message-ID: <20150619093558.GK14386@nuc-i3427.alporthouse.com> (raw)
In-Reply-To: <1434648809-24168-6-git-send-email-arun.siluvery@linux.intel.com>

On Thu, Jun 18, 2015 at 06:33:29PM +0100, Arun Siluvery wrote:
> In Per context w/a batch buffer,
> WaRsRestoreWithPerCtxtBb
> 
> v2: This patches modifies definitions of MI_LOAD_REGISTER_MEM and
> MI_LOAD_REGISTER_REG; Add GEN8 specific defines for these instructions
> so as to not break any future users of existing definitions (Michel)
> 
> v3: Length defined in current definitions of LRM, LRR instructions was specified
> as 0. It seems it is common convention for instructions whose length vary between
> platforms. This is not an issue so far because they are not used anywhere except
> command parser; now that we use in this patch update them with correct length
> and also move them out of command parser placeholder to appropriate place.
> remove unnecessary padding and follow the WA programming sequence exactly
> as mentioned in spec which is essential for this WA (Dave).

Similarly with the indirect ctx from patch 5, having the documentation
that we need scratch_obj in the preamble for these workarounds I think
is worth its weight in the extra typing.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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