From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754267AbbFSJ7o (ORCPT ); Fri, 19 Jun 2015 05:59:44 -0400 Received: from foss.arm.com ([217.140.101.70]:44442 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753246AbbFSJ7f (ORCPT ); Fri, 19 Jun 2015 05:59:35 -0400 Date: Fri, 19 Jun 2015 10:59:32 +0100 From: Will Deacon To: Vineet Gupta Cc: "Peter Zijlstra (Intel)" , lkml , "linux-arch@vger.kernel.org" , "arc-linux-dev@synopsys.com" Subject: Re: [PATCH v2 22/28] ARCv2: STAR 9000837815 workaround hardware exclusive transactions livelock Message-ID: <20150619095932.GC18017@arm.com> References: <20150610110234.GH3644@twins.programming.kicks-ass.net> <1434707726-32624-1-git-send-email-vgupta@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1434707726-32624-1-git-send-email-vgupta@synopsys.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 19, 2015 at 10:55:26AM +0100, Vineet Gupta wrote: > A quad core SMP build could get into hardware livelock with concurrent > LLOCK/SCOND. Workaround that by adding a PREFETCHW which is serialized by > SCU (System Coherency Unit). It brings the cache line in Exclusive state > and makes others invalidate their lines. This gives enough time for > winner to complete the LLOCK/SCOND, before others can get the line back. > > Cc: Peter Zijlstra (Intel) > Signed-off-by: Vineet Gupta > --- > arch/arc/include/asm/atomic.h | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/arch/arc/include/asm/atomic.h b/arch/arc/include/asm/atomic.h > index 20b7dc17979e..03484cb4d16d 100644 > --- a/arch/arc/include/asm/atomic.h > +++ b/arch/arc/include/asm/atomic.h > @@ -23,13 +23,21 @@ > > #define atomic_set(v, i) (((v)->counter) = (i)) > > +#ifdef CONFIG_ISA_ARCV2 > +#define PREFETCHW " prefetchw [%1] \n" > +#else > +#define PREFETCHW > +#endif > + > #define ATOMIC_OP(op, c_op, asm_op) \ > static inline void atomic_##op(int i, atomic_t *v) \ > { \ > unsigned int temp; \ > \ > __asm__ __volatile__( \ > - "1: llock %0, [%1] \n" \ > + "1: \n" \ > + PREFETCHW \ > + " llock %0, [%1] \n" \ > " " #asm_op " %0, %0, %2 \n" \ > " scond %0, [%1] \n" \ > " bnz 1b \n" \ Curious, but are you *sure* the prefetch should be *inside* the loop? On most ll/sc architectures, that's a livelock waiting to happen because you ping-pong the cache-line around in exclusive state. Will