* [PATCH] drm/i915: Update PM interrupts before updating the freq
2015-03-05 4:08 [PATCH] drm/i915: Remove wait for for punit to updates freq deepak.s
@ 2015-03-05 4:08 ` deepak.s
2015-03-05 10:30 ` shuang.he
0 siblings, 1 reply; 6+ messages in thread
From: deepak.s @ 2015-03-05 4:08 UTC (permalink / raw
To: intel-gfx
From: Deepak S <deepak.s@linux.intel.com>
We update the GT PM interrupts mask at the end of set rps. We observed even
though we are requesting a RPn or RP0, there is a chance to get a DOWN or UP
interrupts before interrupts mask. These extra interrupts are simply wasting
cpu cycles. In this patch we mask the interrupts for given freq before
requesting new frequency.
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2e1ed07..bbfe4f0 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3879,12 +3879,12 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
"Odd GPU freq value\n"))
val &= ~1;
+
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
if (val != dev_priv->rps.cur_freq)
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
- I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
-
dev_priv->rps.cur_freq = val;
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
}
--
1.9.1
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Update PM interrupts before updating the freq
2015-03-05 4:08 ` [PATCH] drm/i915: Update PM interrupts before updating the freq deepak.s
@ 2015-03-05 10:30 ` shuang.he
0 siblings, 0 replies; 6+ messages in thread
From: shuang.he @ 2015-03-05 10:30 UTC (permalink / raw
To: shuang.he, ethan.gao, intel-gfx, deepak.s
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5890
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -1 280/280 279/280
ILK -1 308/308 307/308
SNB -18 328/328 310/328
IVB 379/379 379/379
BYT 294/294 294/294
HSW 387/387 387/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_minor-unsync-normal DMESG_WARN(1)PASS(5) DMESG_WARN(1)PASS(1)
*ILK igt_gem_unfence_active_buffers PASS(2) DMESG_WARN(1)PASS(1)
*SNB igt_kms_rotation_crc_primary-rotation NSPT(2)DMESG_WARN(1)PASS(3) DMESG_FAIL(1)NSPT(1)
SNB igt_kms_rotation_crc_sprite-rotation NSPT(2)DMESG_WARN(1)PASS(4) NSPT(2)
SNB igt_pm_rpm_cursor NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_cursor-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_dpms-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_drm-resources-equal NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_fences NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_fences-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-execbuf NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-mmap-cpu NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-mmap-gtt NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-pread NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_i2c NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_modeset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_pci-d3-state NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_rte NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
*BDW igt_gem_gtt_hog PASS(6) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] drm/i915: Update PM interrupts before updating the freq
@ 2015-07-10 13:01 Praveen Paneri
2015-07-11 13:41 ` shuang.he
2015-07-11 16:46 ` Chris Wilson
0 siblings, 2 replies; 6+ messages in thread
From: Praveen Paneri @ 2015-07-10 13:01 UTC (permalink / raw
To: intel-gfx; +Cc: Deepak S, Praveen Paneri
From: Deepak S <deepak.s@intel.com>
Currently we update the freq before masking the interrupts, which can
allow new interrupts to occur before the frequency has changed. These
extra interrupts might waste some cpu cycles. This patch corrects
this by masking interrupts prior to updating the frequency.
Signed-off-by: Deepak S <deepak.s@intel.com>
Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4e24d2b..1082123 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4482,14 +4482,14 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
"Odd GPU freq value\n"))
val &= ~1;
+ I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
+
if (val != dev_priv->rps.cur_freq) {
vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
if (!IS_CHERRYVIEW(dev_priv))
gen6_set_rps_thresholds(dev_priv, val);
}
- I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
-
dev_priv->rps.cur_freq = val;
trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
}
--
1.9.1
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Update PM interrupts before updating the freq
2015-07-10 13:01 [PATCH] drm/i915: Update PM interrupts before updating the freq Praveen Paneri
@ 2015-07-11 13:41 ` shuang.he
2015-07-11 16:46 ` Chris Wilson
1 sibling, 0 replies; 6+ messages in thread
From: shuang.he @ 2015-07-11 13:41 UTC (permalink / raw
To: shuang.he, julianx.dumez, christophe.sureau, lei.a.liu, intel-gfx,
praveen.paneri
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6773
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 303/303 303/303
SNB +3 309/316 312/316
IVB 343/343 343/343
BYT 285/285 285/285
HSW +13 367/381 380/381
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*SNB igt@kms_mmio_vs_cs_flip@setcrtc_vs_cs_flip DMESG_WARN(1) PASS(1)
*SNB igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1)
*SNB igt@pm_rpm@cursor DMESG_WARN(1) PASS(1)
*SNB igt@pm_rpm@cursor-dpms DMESG_FAIL(1) FAIL(1)
*HSW igt@kms_mmio_vs_cs_flip@setplane_vs_cs_flip DMESG_WARN(1) PASS(1)
*HSW igt@pm_lpsp@non-edp DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@debugfs-read DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-idle DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-mmap-gtt DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@gem-pread DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@i2c DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@modeset-non-lpsp DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@modeset-non-lpsp-stress-no-wait DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@pci-d3-state DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@reg-read-ioctl DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@rte DMESG_WARN(1) PASS(1)
*HSW igt@pm_rpm@sysfs-read DMESG_WARN(1) PASS(1)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Update PM interrupts before updating the freq
2015-07-10 13:01 [PATCH] drm/i915: Update PM interrupts before updating the freq Praveen Paneri
2015-07-11 13:41 ` shuang.he
@ 2015-07-11 16:46 ` Chris Wilson
2015-07-13 9:28 ` Daniel Vetter
1 sibling, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2015-07-11 16:46 UTC (permalink / raw
To: Praveen Paneri; +Cc: Deepak S, intel-gfx
On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote:
> From: Deepak S <deepak.s@intel.com>
>
> Currently we update the freq before masking the interrupts, which can
> allow new interrupts to occur before the frequency has changed. These
> extra interrupts might waste some cpu cycles. This patch corrects
> this by masking interrupts prior to updating the frequency.
Well it won't waste CPU cycles as the interrupt is also masked by the
threshold limits, but there should be no harm at all in reordering the
patch so, and it does make a certain amount of sense.
> Signed-off-by: Deepak S <deepak.s@intel.com>
> Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
Quibbling over the language in the changelog aside,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/i915: Update PM interrupts before updating the freq
2015-07-11 16:46 ` Chris Wilson
@ 2015-07-13 9:28 ` Daniel Vetter
0 siblings, 0 replies; 6+ messages in thread
From: Daniel Vetter @ 2015-07-13 9:28 UTC (permalink / raw
To: Chris Wilson, Praveen Paneri, intel-gfx, Deepak S
On Sat, Jul 11, 2015 at 05:46:37PM +0100, Chris Wilson wrote:
> On Fri, Jul 10, 2015 at 06:31:40PM +0530, Praveen Paneri wrote:
> > From: Deepak S <deepak.s@intel.com>
> >
> > Currently we update the freq before masking the interrupts, which can
> > allow new interrupts to occur before the frequency has changed. These
> > extra interrupts might waste some cpu cycles. This patch corrects
> > this by masking interrupts prior to updating the frequency.
>
> Well it won't waste CPU cycles as the interrupt is also masked by the
> threshold limits, but there should be no harm at all in reordering the
> patch so, and it does make a certain amount of sense.
Added and ...
>
> > Signed-off-by: Deepak S <deepak.s@intel.com>
> > Signed-off-by: Praveen Paneri <praveen.paneri@intel.com>
>
> Quibbling over the language in the changelog aside,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-07-13 9:25 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2015-07-10 13:01 [PATCH] drm/i915: Update PM interrupts before updating the freq Praveen Paneri
2015-07-11 13:41 ` shuang.he
2015-07-11 16:46 ` Chris Wilson
2015-07-13 9:28 ` Daniel Vetter
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2015-03-05 4:08 [PATCH] drm/i915: Remove wait for for punit to updates freq deepak.s
2015-03-05 4:08 ` [PATCH] drm/i915: Update PM interrupts before updating the freq deepak.s
2015-03-05 10:30 ` shuang.he
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