From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751731AbbGMO7r (ORCPT ); Mon, 13 Jul 2015 10:59:47 -0400 Received: from mezzanine.sirena.org.uk ([106.187.55.193]:50223 "EHLO mezzanine.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751551AbbGMO7q (ORCPT ); Mon, 13 Jul 2015 10:59:46 -0400 Date: Mon, 13 Jul 2015 15:59:07 +0100 From: Mark Brown To: Mike Looijmans Cc: Ranjit Waghmode , michal.simek@xilinx.com, soren.brinkmann@xilinx.com, dwmw2@infradead.org, computersforpeace@gmail.com, zajec5@gmail.com, marex@denx.de, shijie.huang@intel.com, juhosg@openwrt.org, ben@decadent.org.uk, harinik@xilinx.com, linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, punnaia@xilinx.com, ran27jit@gmail.com, linux-arm-kernel@lists.infradead.org Message-ID: <20150713145907.GF11162@sirena.org.uk> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <559F824B.70409@topic.nl> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="kK9AL8AnBmMfbzhN" Content-Disposition: inline In-Reply-To: <559F824B.70409@topic.nl> X-Cookie: Stay together, drag each other down. User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: 94.175.94.161 X-SA-Exim-Mail-From: broonie@sirena.org.uk Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller X-SA-Exim-Version: 4.2.1 (built Mon, 26 Dec 2011 16:24:06 +0000) X-SA-Exim-Scanned: Yes (on mezzanine.sirena.org.uk) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --kK9AL8AnBmMfbzhN Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: > =EF=BB=BFOn 09-07-15 14:44, Ranjit Waghmode wrote: > >ZynqMP GQSPI controller supports stacked mode with following functionali= ties: > >1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > >2) Separate chip select lines > >3) Shared I/O lines > >4) This mode is targeted for increasing the flash memory and no performa= nce > > improvement when compared with single. > One could also model the stacked mode as having two distinct flash chips > with separate chip selects and shared lines. Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. --kK9AL8AnBmMfbzhN Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJVo9I7AAoJECTWi3JdVIfQio4H/1o3jKiZR03QWE+n+6/R2X3E 9Rgqw1W8K63XeTcpVnO0E5mLv+OQ4WdRg/8CvUExZxkOW5Wm+YGWNjTJ3xzedvtF JrgKNNa/a0U/w9xscFX+x9fhkL7oSVLRg/w3k5s/skDNtfhfGwplzJ5sOxz7jP/5 0H5r6aTuLgchSWzUiSt2mZqwtHRMW0b5WLBR2gil9ez8LtaUZEozOw7wss+RPAH0 MaFFrvC2kr+o+FyVaGfqEjxTWpOCAtEHbvrrfElx4AK7tiUFJ8FoGi+jNmjWA8f7 AdSP+H2QHDkhHCSyGwFxCpAfP72U0fQXLS1EKXCcCQwBSc5jMvtfWSHV5EuuRME= =MTwl -----END PGP SIGNATURE----- --kK9AL8AnBmMfbzhN-- From mboxrd@z Thu Jan 1 00:00:00 1970 From: broonie@kernel.org (Mark Brown) Date: Mon, 13 Jul 2015 15:59:07 +0100 Subject: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller In-Reply-To: <559F824B.70409@topic.nl> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <559F824B.70409@topic.nl> Message-ID: <20150713145907.GF11162@sirena.org.uk> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: > ?On 09-07-15 14:44, Ranjit Waghmode wrote: > >ZynqMP GQSPI controller supports stacked mode with following functionalities: > >1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > >2) Separate chip select lines > >3) Shared I/O lines > >4) This mode is targeted for increasing the flash memory and no performance > > improvement when compared with single. > One could also model the stacked mode as having two distinct flash chips > with separate chip selects and shared lines. Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: Digital signature URL: From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Brown Subject: Re: [RFC PATCH 0/2] spi: add dual parallel & stacked mode support in Zynq MPSoC GQSPI controller Date: Mon, 13 Jul 2015 15:59:07 +0100 Message-ID: <20150713145907.GF11162@sirena.org.uk> References: <1436445895-25504-1-git-send-email-ranjit.waghmode@xilinx.com> <559F824B.70409@topic.nl> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="kK9AL8AnBmMfbzhN" Cc: Ranjit Waghmode , michal.simek-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, soren.brinkmann-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, marex-ynQEQJNshbs@public.gmane.org, shijie.huang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, juhosg-p3rKhJxN3npAfugRpC6u6w@public.gmane.org, ben-/+tVBieCtBitmTQ+vhA3Yw@public.gmane.org, harinik-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, punnaia-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org, ran27jit-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Mike Looijmans Return-path: Content-Disposition: inline In-Reply-To: <559F824B.70409-Oq418RWZeHk@public.gmane.org> Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: --kK9AL8AnBmMfbzhN Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jul 10, 2015 at 10:28:59AM +0200, Mike Looijmans wrote: > =EF=BB=BFOn 09-07-15 14:44, Ranjit Waghmode wrote: > >ZynqMP GQSPI controller supports stacked mode with following functionali= ties: > >1) The Generic Quad-SPI controller also supports two SPI flash memories > > in a shared bus arrangement to reduce IO pin count. > >2) Separate chip select lines > >3) Shared I/O lines > >4) This mode is targeted for increasing the flash memory and no performa= nce > > improvement when compared with single. > One could also model the stacked mode as having two distinct flash chips > with separate chip selects and shared lines. Well, quite. I'm confused about how the above differs from a just a SPI controller with two chip selects which is perfectly standard. --kK9AL8AnBmMfbzhN Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAEBCAAGBQJVo9I7AAoJECTWi3JdVIfQio4H/1o3jKiZR03QWE+n+6/R2X3E 9Rgqw1W8K63XeTcpVnO0E5mLv+OQ4WdRg/8CvUExZxkOW5Wm+YGWNjTJ3xzedvtF JrgKNNa/a0U/w9xscFX+x9fhkL7oSVLRg/w3k5s/skDNtfhfGwplzJ5sOxz7jP/5 0H5r6aTuLgchSWzUiSt2mZqwtHRMW0b5WLBR2gil9ez8LtaUZEozOw7wss+RPAH0 MaFFrvC2kr+o+FyVaGfqEjxTWpOCAtEHbvrrfElx4AK7tiUFJ8FoGi+jNmjWA8f7 AdSP+H2QHDkhHCSyGwFxCpAfP72U0fQXLS1EKXCcCQwBSc5jMvtfWSHV5EuuRME= =MTwl -----END PGP SIGNATURE----- --kK9AL8AnBmMfbzhN-- -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html