From mboxrd@z Thu Jan 1 00:00:00 1970 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 14 Jul 2015 10:35:48 +0200 (CEST) Received: from mailapp01.imgtec.com ([195.59.15.196]:30410 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009261AbbGNIfq1L-lx (ORCPT ); Tue, 14 Jul 2015 10:35:46 +0200 Received: from KLMAIL01.kl.imgtec.org (unknown [192.168.5.35]) by Websense Email Security Gateway with ESMTPS id 9B86FBF8AAE51; Tue, 14 Jul 2015 09:35:38 +0100 (IST) Received: from LEMAIL01.le.imgtec.org (192.168.152.62) by KLMAIL01.kl.imgtec.org (192.168.5.35) with Microsoft SMTP Server (TLS) id 14.3.195.1; Tue, 14 Jul 2015 09:35:40 +0100 Received: from localhost (10.100.200.168) by LEMAIL01.le.imgtec.org (192.168.152.62) with Microsoft SMTP Server (TLS) id 14.3.210.2; Tue, 14 Jul 2015 09:35:39 +0100 Date: Tue, 14 Jul 2015 09:35:39 +0100 From: Paul Burton To: Markos Chandras CC: , Thomas Gleixner , "Jason Cooper" , Andrew Bresticker Subject: Re: [PATCH v2 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Message-ID: <20150714083539.GF2519@NP-P-BURTON> References: <1436434853-30001-11-git-send-email-markos.chandras@imgtec.com> <1436861652-2063-1-git-send-email-markos.chandras@imgtec.com> <20150714083019.GD2519@NP-P-BURTON> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <20150714083019.GD2519@NP-P-BURTON> User-Agent: Mutt/1.5.23 (2014-03-12) X-Originating-IP: [10.100.200.168] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 48260 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: paul.burton@imgtec.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips On Tue, Jul 14, 2015 at 09:30:19AM +0100, Paul Burton wrote: > On Tue, Jul 14, 2015 at 09:14:12AM +0100, Markos Chandras wrote: > > Previously, the CM accessors were only accessing CM registers as u32 > > types instead of using the native CM register with. However, newer CMs > > may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs > > (CM3) hold all the useful configuration bits in the lower half of the > > 64-bit registers (at least most of them) so they can still be accessed > > using the current 32-bit accessors. > > > > Cc: Thomas Gleixner > > Cc: Jason Cooper > > Cc: Andrew Bresticker > > Cc: Paul Burton > > Signed-off-by: Markos Chandras > > --- > > Changes since v1 > > - Use 32-bit CM I/O on 32-bit kernels > > A concern I have, but haven't yet drank enough coffee to think through > fully, is whether this will work on big endian systems. These are 64b > addresses and you're writing 32b to their addresses which I suspect may > go horribly wrong. Should be: "These are 64b registers and you're writing 32b to their addresses" Apparently I haven't drunk enouugh coffee to formulate sentences yet either ;) Thanks, Paul From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailapp01.imgtec.com ([195.59.15.196]:30410 "EHLO mailapp01.imgtec.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S27009261AbbGNIfq1L-lx (ORCPT ); Tue, 14 Jul 2015 10:35:46 +0200 Date: Tue, 14 Jul 2015 09:35:39 +0100 From: Paul Burton Subject: Re: [PATCH v2 10/19] MIPS: asm: mips-cm: Extend CM accessors for 64-bit CPUs Message-ID: <20150714083539.GF2519@NP-P-BURTON> References: <1436434853-30001-11-git-send-email-markos.chandras@imgtec.com> <1436861652-2063-1-git-send-email-markos.chandras@imgtec.com> <20150714083019.GD2519@NP-P-BURTON> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <20150714083019.GD2519@NP-P-BURTON> Return-Path: Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-subscribe: List-owner: List-post: List-archive: To: Markos Chandras Cc: linux-mips@linux-mips.org, Thomas Gleixner , Jason Cooper , Andrew Bresticker Message-ID: <20150714083539.k_UA2uVBeBj9gA_bM-62yU-WKRSoRG2y8AkeOfLCnto@z> On Tue, Jul 14, 2015 at 09:30:19AM +0100, Paul Burton wrote: > On Tue, Jul 14, 2015 at 09:14:12AM +0100, Markos Chandras wrote: > > Previously, the CM accessors were only accessing CM registers as u32 > > types instead of using the native CM register with. However, newer CMs > > may actually be 64-bit on MIPS64 cores. Fortunately, current 64-bit CMs > > (CM3) hold all the useful configuration bits in the lower half of the > > 64-bit registers (at least most of them) so they can still be accessed > > using the current 32-bit accessors. > > > > Cc: Thomas Gleixner > > Cc: Jason Cooper > > Cc: Andrew Bresticker > > Cc: Paul Burton > > Signed-off-by: Markos Chandras > > --- > > Changes since v1 > > - Use 32-bit CM I/O on 32-bit kernels > > A concern I have, but haven't yet drank enough coffee to think through > fully, is whether this will work on big endian systems. These are 64b > addresses and you're writing 32b to their addresses which I suspect may > go horribly wrong. Should be: "These are 64b registers and you're writing 32b to their addresses" Apparently I haven't drunk enouugh coffee to formulate sentences yet either ;) Thanks, Paul