From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753738AbbIKR5I (ORCPT ); Fri, 11 Sep 2015 13:57:08 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:38268 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753670AbbIKR5F (ORCPT ); Fri, 11 Sep 2015 13:57:05 -0400 Date: Fri, 11 Sep 2015 18:57:00 +0100 From: Lee Jones To: Peter Griffin Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@gmail.com, maxime.coquelin@st.com, patrice.chotard@st.com, devicetree@vger.kernel.org, Giuseppe Cavallaro Subject: Re: [PATCH 10/11] ARM: DT: STiH407: Add RMII pinctrl support Message-ID: <20150911175700.GH18779@x1> References: <1441991194-11948-1-git-send-email-peter.griffin@linaro.org> <1441991194-11948-11-git-send-email-peter.griffin@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1441991194-11948-11-git-send-email-peter.griffin@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 11 Sep 2015, Peter Griffin wrote: > This patch adds the RMII pinctrl support for the Synopsys > MAC on STiH407 SoCs. > > Signed-off-by: Giuseppe Cavallaro > Signed-off-by: Peter Griffin > --- > arch/arm/boot/dts/stih407-pinctrl.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) Acked-by: Lee Jones > diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi > index 473f2ea..e80cac5 100644 > --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi > @@ -256,6 +256,33 @@ > phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; > }; > }; > + > + pinctrl_rmii1: rmii1-0 { > + st,pins { > + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; > + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; > + mdint = <&pio1 3 ALT1 IN BYPASS 0>; > + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; > + }; > + }; > + > + pinctrl_rmii1_phyclk: rmii1_phyclk { > + st,pins { > + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; > + }; > + }; > + > + pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { > + st,pins { > + phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; > + }; > + }; > }; > > pwm1 { -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Fri, 11 Sep 2015 18:57:00 +0100 Subject: [PATCH 10/11] ARM: DT: STiH407: Add RMII pinctrl support In-Reply-To: <1441991194-11948-11-git-send-email-peter.griffin@linaro.org> References: <1441991194-11948-1-git-send-email-peter.griffin@linaro.org> <1441991194-11948-11-git-send-email-peter.griffin@linaro.org> Message-ID: <20150911175700.GH18779@x1> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, 11 Sep 2015, Peter Griffin wrote: > This patch adds the RMII pinctrl support for the Synopsys > MAC on STiH407 SoCs. > > Signed-off-by: Giuseppe Cavallaro > Signed-off-by: Peter Griffin > --- > arch/arm/boot/dts/stih407-pinctrl.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) Acked-by: Lee Jones > diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi > index 473f2ea..e80cac5 100644 > --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi > +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi > @@ -256,6 +256,33 @@ > phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; > }; > }; > + > + pinctrl_rmii1: rmii1-0 { > + st,pins { > + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; > + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; > + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; > + mdint = <&pio1 3 ALT1 IN BYPASS 0>; > + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_B>; > + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; > + }; > + }; > + > + pinctrl_rmii1_phyclk: rmii1_phyclk { > + st,pins { > + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; > + }; > + }; > + > + pinctrl_rmii1_phyclk_ext: rmii1_phyclk_ext { > + st,pins { > + phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>; > + }; > + }; > }; > > pwm1 { -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org ? Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog