From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933693AbbIVN3i (ORCPT ); Tue, 22 Sep 2015 09:29:38 -0400 Received: from mail-ob0-f179.google.com ([209.85.214.179]:35330 "EHLO mail-ob0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933111AbbIVN3g (ORCPT ); Tue, 22 Sep 2015 09:29:36 -0400 Date: Tue, 22 Sep 2015 21:29:14 +0800 From: Boqun Feng To: Martin Schwidefsky Cc: paulmck@linux.vnet.ibm.com, Peter Zijlstra , Davidlohr Bueso , Ingo Molnar , Thomas Gleixner , linux-kernel@vger.kernel.org, Davidlohr Bueso , heiko.carstens@de.ibm.com Subject: Re: [PATCH -tip 2/3] sched/wake_q: Relax to acquire semantics Message-ID: <20150922132913.GA27867@fixme-laptop.cn.ibm.com> References: <20150915140922.GG4029@linux.vnet.ibm.com> <20150915141439.GE16853@twins.programming.kicks-ass.net> <20150915153448.GI4029@linux.vnet.ibm.com> <20150915163028.GG16853@twins.programming.kicks-ass.net> <20150915170941.GL4029@linux.vnet.ibm.com> <20150918214120.GA4405@linux.vnet.ibm.com> <20150921112252.3c2937e1@mschwide> <20150922122735.14f3c573@mschwide> <20150922122326.GA1032@fixme-laptop.cn.ibm.com> <20150922145136.761241da@mschwide> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="WIyZ46R2i8wDzkSu" Content-Disposition: inline In-Reply-To: <20150922145136.761241da@mschwide> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --WIyZ46R2i8wDzkSu Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Sep 22, 2015 at 02:51:36PM +0200, Martin Schwidefsky wrote: > On Tue, 22 Sep 2015 20:23:26 +0800 > Boqun Feng wrote: >=20 > > Hi Martin, > >=20 > > On Tue, Sep 22, 2015 at 12:27:35PM +0200, Martin Schwidefsky wrote: > > > On Mon, 21 Sep 2015 11:22:52 +0200 > > > Martin Schwidefsky wrote: > > >=20 > > > > On Fri, 18 Sep 2015 14:41:20 -0700 > > > > "Paul E. McKenney" wrote: > > > >=20 > > > > > On Tue, Sep 15, 2015 at 10:09:41AM -0700, Paul E. McKenney wrote: > > > > > > On Tue, Sep 15, 2015 at 06:30:28PM +0200, Peter Zijlstra wrote: > > > > > > > On Tue, Sep 15, 2015 at 08:34:48AM -0700, Paul E. McKenney wr= ote: > > > > > > > > On Tue, Sep 15, 2015 at 04:14:39PM +0200, Peter Zijlstra wr= ote: > > > > > > > > > On Tue, Sep 15, 2015 at 07:09:22AM -0700, Paul E. McKenne= y wrote: > > > > > > > > > > On Tue, Sep 15, 2015 at 02:48:00PM +0200, Peter Zijlstr= a wrote: > > > > > > > > > > > On Tue, Sep 15, 2015 at 05:41:42AM -0700, Paul E. McK= enney wrote: > > > > > > > > > > > > > Never mind, the PPC people will implement this wi= th lwsync and that is > > > > > > > > > > > > > very much not transitive IIRC. > > > > > > > > > > > >=20 > > > > > > > > > > > > I am probably lost on context, but... > > > > > > > > > > > >=20 > > > > > > > > > > > > It turns out that lwsync is transitive in special c= ases. One of them > > > > > > > > > > > > is a series of release-acquire pairs, which can ext= end indefinitely. > > > > > > > > > > > >=20 > > > > > > > > > > > > Does that help in this case? > > > > > > > > > > >=20 > > > > > > > > > > > Probably not, but good to know. I still don't think w= e want to rely on > > > > > > > > > > > ACQUIRE/RELEASE being transitive in general though. > > > > > > > > > >=20 > > > > > > > > > > OK, I will bite... Why not? > > > > > > > > >=20 > > > > > > > > > It would mean us reviewing all archs (again) and document= ing it I > > > > > > > > > suppose. Which is of course entirely possible. > > > > > > > > >=20 > > > > > > > > > That said, I don't think the case at hand requires it, so= lets postpone > > > > > > > > > this for now ;-) > > > > > > > >=20 > > > > > > > > True enough, but in my experience smp_store_release() and > > > > > > > > smp_load_acquire() are a -lot- easier to use than other bar= riers, > > > > > > > > and transitivity will help promote their use. So... > > > > > > > >=20 > > > > > > > > All the TSO architectures (x86, s390, SPARC, HPPA, ...) sup= port transitive > > > > > > > > smp_store_release()/smp_load_acquire() via their native ord= ering in > > > > > > > > combination with barrier() macros. x86 with CONFIG_X86_PPR= O_FENCE=3Dy, > > > > > > > > which is not TSO, uses an mfence instruction. Power suppor= ts this via > > > > > > > > lwsync's partial cumulativity. ARM64 supports it in SMP vi= a the new ldar > > > > > > > > and stlr instructions (in non-SMP, it uses barrier(), which= suffices > > > > > > > > in that case). IA64 supports this via total ordering of al= l release > > > > > > > > instructions in theory and by the actual full-barrier imple= mentation > > > > > > > > in practice (and the fact that gcc emits st.rel and ld.acq = instructions > > > > > > > > for volatile stores and loads). All other architectures us= e smp_mb(), > > > > > > > > which is transitive. > > > > > > > >=20 > > > > > > > > Did I miss anything? > > > > > > >=20 > > > > > > > I think that about covers it.. the only odd duckling might be= s390 which > > > > > > > is documented as TSO but recently grew smp_mb__{before,after}= _atomic(), > > > > > > > which seems to confuse matters. > > > > > >=20 > > > > > > Fair point, adding Martin and Heiko on CC for their thoughts. > > > >=20 > > > > Well we always had the full memory barrier for the various versions= of > > > > smp_mb__xxx, they just have moved around and renamed several times. > > > >=20 > > > > After discussing this with Heiko we came to the conclusion that we = can use > > > > a simple barrier() for smp_mb__before_atomic() and smp_mb__after_at= omic(). > > > >=20 > > > > > > It looks like this applies to recent mainframes that have new a= tomic > > > > > > instructions, which, yes, might need something to make them wor= k with > > > > > > fully transitive smp_load_acquire() and smp_store_release(). > > > > > >=20 > > > > > > Martin, Heiko, the question is whether or not the current s390 > > > > > > smp_store_release() and smp_load_acquire() can be transitive. > > > > > > For example, if all the Xi variables below are initially zero, > > > > > > is it possible for all the r0, r1, r2, ... rN variables to > > > > > > have the value 1 at the end of the test. > > > > >=20 > > > > > Right... This time actually adding Martin and Heiko on CC... > > > > >=20 > > > > > Thanx, Paul > > > > >=20 > > > > > > CPU 0 > > > > > > r0 =3D smp_load_acquire(&X0); > > > > > > smp_store_release(&X1, 1); > > > > > >=20 > > > > > > CPU 1 > > > > > > r1 =3D smp_load_acquire(&X1); > > > > > > smp_store_release(&X2, 1); > > > > > >=20 > > > > > > CPU 2 > > > > > > r2 =3D smp_load_acquire(&X2); > > > > > > smp_store_release(&X3, 1); > > > > > >=20 > > > > > > ... > > > > > >=20 > > > > > > CPU N > > > > > > rN =3D smp_load_acquire(&XN); > > > > > > smp_store_release(&X0, 1); > > > > > >=20 > > > > > > If smp_store_release() and smp_load_acquire() are transitive, t= he > > > > > > answer would be "no". > > > >=20 > > > > The answer is "no". Christian recently summarized what the principl= es of > > > > operation has to say about the CPU read / write behavior. If you co= nsider > > > > the sequential order of instructions then > > > >=20 > > > > 1) reads are in order > > > > 2) writes are in order > > > > 3) reads can happen earlier > > > > 4) writes can happen later > > >=20 > > > Correction. The principles of operation states this: > > >=20 > > > "A storage-operand store specified by one instruction appears to prec= ede > > > all storage-operand stores specified by conceptually subsequent instr= uctions, > > > but it does not necessarily precede storage-operand fetches specified= by > > > conceptually subsequent instructions. However, a storage-operand store > > > appears to precede a conceptually subsequent storage-operand fetch fr= om the > > > same main-storage location." > > >=20 Confused... IIUC, the previous paragraph actually means that a STORE-LOAD pair can be reordered. But the below reasoning is saying that a LOAD-STORE pair can be reordered. Do I miss something here? > > > As observed by other CPUs a write to one memory location can "overtak= e" a > > > read of another memory location if there is no explicit memory-barrier > > > between the load and the store instruction. > > >=20 > > > In the above example X0, X1, ... XN are different memory locations, so > > > architecturally the answer is "yes", all r0, r1, ... rN variables can= have > > > the value of 1 after the test. I doubt that any existing machine will > > > show this behavior though. > > >=20 > >=20 > > Just be curious, how about when N =3D=3D 1? The test then becomes: > >=20 > > CPU 0 > > r0 =3D smp_load_acquire(&X0); > > smp_store_release(&X1,1); > >=20 > > CPU 1 > > r1 =3D smp_load_acquire(&X1); > > smp_store_release(&X0,1); > >=20 > > Is it possible that r0 =3D=3D 1 and r1 =3D=3D 1 at the end, due to the = same > > reason? >=20 > Yes, that is possible for the same reason. To change that we would have > to replace the barrier() in smp_load_acquire/smp_store_release with > smp_mb(). >=20 I thought that s390 is TSO, so this is prohibitted. If that is possible, I think, that means the current implementation of smp_load_acquire and smp_store_release on s390 is incorrect... Regards, Boqun --WIyZ46R2i8wDzkSu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQEcBAABCAAGBQJWAVeNAAoJEEl56MO1B/q4Ln4H/jJUcupqa5LfOdkjhvVbg8uC gw61h4N69LM02BHZl+8Hpt9xsYv12I+SsnPAguZn7ENDtAniF+Tftf6ELZqTVAfa HlP1NBzdQmeJXBYA+1p+6mApi5rr/c9cfN3gngQPjNgmzIw3f+X6AqmDMijbuO9o pAR6NtNyujdTXRRrzgV9lozvFAt8zi6xeyiaWP1l+zflU5GV3HEd/I1dHVJW6zOX 41CVaID3gKti1vDTmtu/KgNSfSUXRLmonwL710/O52ibiPj+cVnZqc8eV6CXU9CN okgJl6HSd2AvQrt+2xzM37vr4bKdCEovFTmD34r+D3v8q02qyvgfYQEawi3Y29Y= =r0cQ -----END PGP SIGNATURE----- --WIyZ46R2i8wDzkSu--