From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933033AbbIVMvy (ORCPT ); Tue, 22 Sep 2015 08:51:54 -0400 Received: from e06smtp09.uk.ibm.com ([195.75.94.105]:56890 "EHLO e06smtp09.uk.ibm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751930AbbIVMvx (ORCPT ); Tue, 22 Sep 2015 08:51:53 -0400 X-Helo: d06dlp03.portsmouth.uk.ibm.com X-MailFrom: schwidefsky@de.ibm.com X-RcptTo: linux-kernel@vger.kernel.org Date: Tue, 22 Sep 2015 14:51:36 +0200 From: Martin Schwidefsky To: Boqun Feng Cc: paulmck@linux.vnet.ibm.com, Peter Zijlstra , Davidlohr Bueso , Ingo Molnar , Thomas Gleixner , linux-kernel@vger.kernel.org, Davidlohr Bueso , heiko.carstens@de.ibm.com Subject: Re: [PATCH -tip 2/3] sched/wake_q: Relax to acquire semantics Message-ID: <20150922145136.761241da@mschwide> In-Reply-To: <20150922122326.GA1032@fixme-laptop.cn.ibm.com> References: <20150915124142.GF4029@linux.vnet.ibm.com> <20150915124800.GB16853@twins.programming.kicks-ass.net> <20150915140922.GG4029@linux.vnet.ibm.com> <20150915141439.GE16853@twins.programming.kicks-ass.net> <20150915153448.GI4029@linux.vnet.ibm.com> <20150915163028.GG16853@twins.programming.kicks-ass.net> <20150915170941.GL4029@linux.vnet.ibm.com> <20150918214120.GA4405@linux.vnet.ibm.com> <20150921112252.3c2937e1@mschwide> <20150922122735.14f3c573@mschwide> <20150922122326.GA1032@fixme-laptop.cn.ibm.com> X-Mailer: Claws Mail 3.9.3 (GTK+ 2.24.23; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; boundary="Sig_/AsG7+f5v7QM9+cS3vFodrxE"; protocol="application/pgp-signature" X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 15092212-0037-0000-0000-000003FD81C8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --Sig_/AsG7+f5v7QM9+cS3vFodrxE Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Tue, 22 Sep 2015 20:23:26 +0800 Boqun Feng wrote: > Hi Martin, >=20 > On Tue, Sep 22, 2015 at 12:27:35PM +0200, Martin Schwidefsky wrote: > > On Mon, 21 Sep 2015 11:22:52 +0200 > > Martin Schwidefsky wrote: > >=20 > > > On Fri, 18 Sep 2015 14:41:20 -0700 > > > "Paul E. McKenney" wrote: > > >=20 > > > > On Tue, Sep 15, 2015 at 10:09:41AM -0700, Paul E. McKenney wrote: > > > > > On Tue, Sep 15, 2015 at 06:30:28PM +0200, Peter Zijlstra wrote: > > > > > > On Tue, Sep 15, 2015 at 08:34:48AM -0700, Paul E. McKenney wrot= e: > > > > > > > On Tue, Sep 15, 2015 at 04:14:39PM +0200, Peter Zijlstra wrot= e: > > > > > > > > On Tue, Sep 15, 2015 at 07:09:22AM -0700, Paul E. McKenney = wrote: > > > > > > > > > On Tue, Sep 15, 2015 at 02:48:00PM +0200, Peter Zijlstra = wrote: > > > > > > > > > > On Tue, Sep 15, 2015 at 05:41:42AM -0700, Paul E. McKen= ney wrote: > > > > > > > > > > > > Never mind, the PPC people will implement this with= lwsync and that is > > > > > > > > > > > > very much not transitive IIRC. > > > > > > > > > > >=20 > > > > > > > > > > > I am probably lost on context, but... > > > > > > > > > > >=20 > > > > > > > > > > > It turns out that lwsync is transitive in special cas= es. One of them > > > > > > > > > > > is a series of release-acquire pairs, which can exten= d indefinitely. > > > > > > > > > > >=20 > > > > > > > > > > > Does that help in this case? > > > > > > > > > >=20 > > > > > > > > > > Probably not, but good to know. I still don't think we = want to rely on > > > > > > > > > > ACQUIRE/RELEASE being transitive in general though. > > > > > > > > >=20 > > > > > > > > > OK, I will bite... Why not? > > > > > > > >=20 > > > > > > > > It would mean us reviewing all archs (again) and documentin= g it I > > > > > > > > suppose. Which is of course entirely possible. > > > > > > > >=20 > > > > > > > > That said, I don't think the case at hand requires it, so l= ets postpone > > > > > > > > this for now ;-) > > > > > > >=20 > > > > > > > True enough, but in my experience smp_store_release() and > > > > > > > smp_load_acquire() are a -lot- easier to use than other barri= ers, > > > > > > > and transitivity will help promote their use. So... > > > > > > >=20 > > > > > > > All the TSO architectures (x86, s390, SPARC, HPPA, ...) suppo= rt transitive > > > > > > > smp_store_release()/smp_load_acquire() via their native order= ing in > > > > > > > combination with barrier() macros. x86 with CONFIG_X86_PPRO_= FENCE=3Dy, > > > > > > > which is not TSO, uses an mfence instruction. Power supports= this via > > > > > > > lwsync's partial cumulativity. ARM64 supports it in SMP via = the new ldar > > > > > > > and stlr instructions (in non-SMP, it uses barrier(), which s= uffices > > > > > > > in that case). IA64 supports this via total ordering of all = release > > > > > > > instructions in theory and by the actual full-barrier impleme= ntation > > > > > > > in practice (and the fact that gcc emits st.rel and ld.acq in= structions > > > > > > > for volatile stores and loads). All other architectures use = smp_mb(), > > > > > > > which is transitive. > > > > > > >=20 > > > > > > > Did I miss anything? > > > > > >=20 > > > > > > I think that about covers it.. the only odd duckling might be s= 390 which > > > > > > is documented as TSO but recently grew smp_mb__{before,after}_a= tomic(), > > > > > > which seems to confuse matters. > > > > >=20 > > > > > Fair point, adding Martin and Heiko on CC for their thoughts. > > >=20 > > > Well we always had the full memory barrier for the various versions of > > > smp_mb__xxx, they just have moved around and renamed several times. > > >=20 > > > After discussing this with Heiko we came to the conclusion that we ca= n use > > > a simple barrier() for smp_mb__before_atomic() and smp_mb__after_atom= ic(). > > >=20 > > > > > It looks like this applies to recent mainframes that have new ato= mic > > > > > instructions, which, yes, might need something to make them work = with > > > > > fully transitive smp_load_acquire() and smp_store_release(). > > > > >=20 > > > > > Martin, Heiko, the question is whether or not the current s390 > > > > > smp_store_release() and smp_load_acquire() can be transitive. > > > > > For example, if all the Xi variables below are initially zero, > > > > > is it possible for all the r0, r1, r2, ... rN variables to > > > > > have the value 1 at the end of the test. > > > >=20 > > > > Right... This time actually adding Martin and Heiko on CC... > > > >=20 > > > > Thanx, Paul > > > >=20 > > > > > CPU 0 > > > > > r0 =3D smp_load_acquire(&X0); > > > > > smp_store_release(&X1, 1); > > > > >=20 > > > > > CPU 1 > > > > > r1 =3D smp_load_acquire(&X1); > > > > > smp_store_release(&X2, 1); > > > > >=20 > > > > > CPU 2 > > > > > r2 =3D smp_load_acquire(&X2); > > > > > smp_store_release(&X3, 1); > > > > >=20 > > > > > ... > > > > >=20 > > > > > CPU N > > > > > rN =3D smp_load_acquire(&XN); > > > > > smp_store_release(&X0, 1); > > > > >=20 > > > > > If smp_store_release() and smp_load_acquire() are transitive, the > > > > > answer would be "no". > > >=20 > > > The answer is "no". Christian recently summarized what the principles= of > > > operation has to say about the CPU read / write behavior. If you cons= ider > > > the sequential order of instructions then > > >=20 > > > 1) reads are in order > > > 2) writes are in order > > > 3) reads can happen earlier > > > 4) writes can happen later > >=20 > > Correction. The principles of operation states this: > >=20 > > "A storage-operand store specified by one instruction appears to precede > > all storage-operand stores specified by conceptually subsequent instruc= tions, > > but it does not necessarily precede storage-operand fetches specified by > > conceptually subsequent instructions. However, a storage-operand store > > appears to precede a conceptually subsequent storage-operand fetch from= the > > same main-storage location." > >=20 > > As observed by other CPUs a write to one memory location can "overtake"= a > > read of another memory location if there is no explicit memory-barrier > > between the load and the store instruction. > >=20 > > In the above example X0, X1, ... XN are different memory locations, so > > architecturally the answer is "yes", all r0, r1, ... rN variables can h= ave > > the value of 1 after the test. I doubt that any existing machine will > > show this behavior though. > >=20 >=20 > Just be curious, how about when N =3D=3D 1? The test then becomes: >=20 > CPU 0 > r0 =3D smp_load_acquire(&X0); > smp_store_release(&X1,1); >=20 > CPU 1 > r1 =3D smp_load_acquire(&X1); > smp_store_release(&X0,1); >=20 > Is it possible that r0 =3D=3D 1 and r1 =3D=3D 1 at the end, due to the sa= me > reason? Yes, that is possible for the same reason. To change that we would have to replace the barrier() in smp_load_acquire/smp_store_release with smp_mb(). --=20 blue skies, Martin. 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