* [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
@ 2016-03-15 23:37 Dongwon Kim
2016-03-16 9:01 ` Imre Deak
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Dongwon Kim @ 2016-03-15 23:37 UTC (permalink / raw
To: intel-gfx; +Cc: Dongwon Kim
For BXT, Polarity of PORT_PLL_REF_SEL is reversed in
its description in Bspec. This bit should be set for
"Non-SSC".
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 4b636c4..d55b308 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1285,7 +1285,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
- temp &= ~PORT_PLL_REF_SEL;
+ temp |= PORT_PLL_REF_SEL;
/* Non-SSC reference */
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-15 23:37 [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit Dongwon Kim
@ 2016-03-16 9:01 ` Imre Deak
2016-03-16 11:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2016-03-16 9:01 UTC (permalink / raw
To: Dongwon Kim, intel-gfx; +Cc: Runyan, Arthur J
On Tue, 2016-03-15 at 16:37 -0700, Dongwon Kim wrote:
> For BXT, Polarity of PORT_PLL_REF_SEL is reversed in
> its description in Bspec. This bit should be set for
> "Non-SSC".
Thanks for the patch.
In the future please also mention where the change originates from, in
this case it is a recent update to the specification (which in turn is
based on an internal report of an HDMI HW problem). Looking at that
internal report (HSD) it says it only affects BXT-P but not BXT-T, so
do we know that the meaning of the bit is inverted on both?
Adding Art for more info.
--Imre
> Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 4b636c4..d55b308 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1285,7 +1285,7 @@ static void bxt_ddi_pll_enable(struct
> drm_i915_private *dev_priv,
> enum port port = (enum port)pll->id; /* 1:1 port->PLL
> mapping */
>
> temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> - temp &= ~PORT_PLL_REF_SEL;
> + temp |= PORT_PLL_REF_SEL;
> /* Non-SSC reference */
> I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-15 23:37 [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit Dongwon Kim
2016-03-16 9:01 ` Imre Deak
@ 2016-03-16 11:58 ` Patchwork
2016-03-16 16:58 ` dw kim
2016-03-17 1:06 ` [PATCH] " Dongwon Kim
2016-03-17 13:03 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2) Patchwork
3 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2016-03-16 11:58 UTC (permalink / raw
To: Dongwon Kim; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
URL : https://patchwork.freedesktop.org/series/4491/
State : failure
== Summary ==
Series 4491v1 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
http://patchwork.freedesktop.org/api/1.0/series/4491/revisions/1/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-copy:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (skl-nuci5)
Test gem_ringfill:
Subgroup basic-default-s3:
dmesg-warn -> PASS (skl-i5k-2)
pass -> DMESG-WARN (skl-nuci5)
Test kms_flip:
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (snb-x220t)
dmesg-warn -> PASS (hsw-brixbox)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-a:
dmesg-warn -> PASS (bdw-nuci7)
Test pm_rpm:
Subgroup basic-pci-d3-state:
dmesg-warn -> PASS (bsw-nuc-2)
pass -> DMESG-WARN (hsw-brixbox)
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
hsw-brixbox total:194 pass:171 dwarn:1 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:177 dwarn:0 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:181 dwarn:2 dfail:0 fail:0 skip:11
snb-x220t total:194 pass:158 dwarn:1 dfail:0 fail:2 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1611/
9f8709ffd099e85e5e116ed7d09f1b8009f40847 drm-intel-nightly: 2016y-03m-16d-10h-30m-26s UTC integration manifest
a5aa41667c7524d0df92320530f11dc283c6c95e drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-16 11:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-03-16 16:58 ` dw kim
0 siblings, 0 replies; 11+ messages in thread
From: dw kim @ 2016-03-16 16:58 UTC (permalink / raw
To: intel-gfx
This error doesn't seem to be related to this specific patch.
Similar issue was already filed in Bugzilla a week ago at
https://bugs.freedesktop.org/show_bug.cgi?id=94294
On Wed, Mar 16, 2016 at 11:58:28AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
> URL : https://patchwork.freedesktop.org/series/4491/
> State : failure
>
> == Summary ==
>
> Series 4491v1 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
> http://patchwork.freedesktop.org/api/1.0/series/4491/revisions/1/mbox/
>
> Test gem_mmap_gtt:
> Subgroup basic-small-copy:
> dmesg-warn -> PASS (bsw-nuc-2)
> pass -> DMESG-WARN (skl-nuci5)
> Test gem_ringfill:
> Subgroup basic-default-s3:
> dmesg-warn -> PASS (skl-i5k-2)
> pass -> DMESG-WARN (skl-nuci5)
> Test kms_flip:
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (snb-x220t)
> dmesg-warn -> PASS (hsw-brixbox)
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-a:
> dmesg-warn -> PASS (bdw-nuci7)
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> dmesg-warn -> PASS (bsw-nuc-2)
> pass -> DMESG-WARN (hsw-brixbox)
>
> bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
> bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
> bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
> byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
> hsw-brixbox total:194 pass:171 dwarn:1 dfail:0 fail:0 skip:22
> hsw-gt2 total:194 pass:177 dwarn:0 dfail:0 fail:0 skip:17
> ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
> skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-nuci5 total:194 pass:181 dwarn:2 dfail:0 fail:0 skip:11
> snb-x220t total:194 pass:158 dwarn:1 dfail:0 fail:2 skip:33
>
> Results at /archive/results/CI_IGT_test/Patchwork_1611/
>
> 9f8709ffd099e85e5e116ed7d09f1b8009f40847 drm-intel-nightly: 2016y-03m-16d-10h-30m-26s UTC integration manifest
> a5aa41667c7524d0df92320530f11dc283c6c95e drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-15 23:37 [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit Dongwon Kim
2016-03-16 9:01 ` Imre Deak
2016-03-16 11:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-03-17 1:06 ` Dongwon Kim
2016-03-22 9:10 ` Imre Deak
2016-04-11 10:00 ` Imre Deak
2016-03-17 13:03 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2) Patchwork
3 siblings, 2 replies; 11+ messages in thread
From: Dongwon Kim @ 2016-03-17 1:06 UTC (permalink / raw
To: intel-gfx; +Cc: Dongwon Kim
For BXT, description of polarities of PORT_PLL_REF_SEL
has been reversed for newer Gen9LP steppings according to the
recent update in Bspec. This bit now should be set for
"Non-SSC" mode for all Gen9LP starting from B0 stepping.
v2: Only B0 and newer stepping should be affected by this
change.
Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 4b636c4..c84589e 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1285,7 +1285,15 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
- temp &= ~PORT_PLL_REF_SEL;
+ /*
+ * Definition of each bit polarity has been changed
+ * after A1 stepping
+ */
+ if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
+ temp &= ~PORT_PLL_REF_SEL;
+ else
+ temp |= PORT_PLL_REF_SEL;
+
/* Non-SSC reference */
I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2)
2016-03-15 23:37 [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit Dongwon Kim
` (2 preceding siblings ...)
2016-03-17 1:06 ` [PATCH] " Dongwon Kim
@ 2016-03-17 13:03 ` Patchwork
2016-03-17 18:05 ` dw kim
3 siblings, 1 reply; 11+ messages in thread
From: Patchwork @ 2016-03-17 13:03 UTC (permalink / raw
To: Dongwon Kim; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2)
URL : https://patchwork.freedesktop.org/series/4491/
State : failure
== Summary ==
Series 4491v2 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
http://patchwork.freedesktop.org/api/1.0/series/4491/revisions/2/mbox/
Test drv_module_reload_basic:
dmesg-warn -> PASS (hsw-gt2)
Test gem_ringfill:
Subgroup basic-default-s3:
dmesg-warn -> PASS (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (bdw-ultra)
Subgroup basic-flip-vs-wf_vblank:
fail -> PASS (snb-x220t)
Subgroup basic-plain-flip:
pass -> DMESG-WARN (hsw-gt2)
dmesg-warn -> PASS (hsw-brixbox)
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
pass -> SKIP (snb-x220t)
Test kms_pipe_crc_basic:
Subgroup read-crc-pipe-b-frame-sequence:
dmesg-warn -> PASS (snb-x220t)
Subgroup read-crc-pipe-c-frame-sequence:
dmesg-warn -> PASS (hsw-gt2)
Test pm_rpm:
Subgroup basic-pci-d3-state:
fail -> DMESG-FAIL (snb-x220t)
Subgroup basic-rte:
dmesg-warn -> PASS (hsw-brixbox)
bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
snb-x220t total:194 pass:159 dwarn:0 dfail:1 fail:0 skip:34
Results at /archive/results/CI_IGT_test/Patchwork_1628/
8a9a911d489fe160df173580277983dac5952ed0 drm-intel-nightly: 2016y-03m-17d-10h-02m-10s UTC integration manifest
f432d2fe29fb024ac515e2ad2a7a8bb9700e6c70 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2)
2016-03-17 13:03 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2) Patchwork
@ 2016-03-17 18:05 ` dw kim
2016-04-11 10:10 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: dw kim @ 2016-03-17 18:05 UTC (permalink / raw
To: intel-gfx
On Thu, Mar 17, 2016 at 01:03:36PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2)
> URL : https://patchwork.freedesktop.org/series/4491/
> State : failure
>
> == Summary ==
>
> Series 4491v2 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
> http://patchwork.freedesktop.org/api/1.0/series/4491/revisions/2/mbox/
>
> Test drv_module_reload_basic:
> dmesg-warn -> PASS (hsw-gt2)
> Test gem_ringfill:
> Subgroup basic-default-s3:
> dmesg-warn -> PASS (bsw-nuc-2)
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> dmesg-warn -> PASS (bdw-ultra)
> Subgroup basic-flip-vs-wf_vblank:
> fail -> PASS (snb-x220t)
> Subgroup basic-plain-flip:
> pass -> DMESG-WARN (hsw-gt2)
> dmesg-warn -> PASS (hsw-brixbox)
> Test kms_force_connector_basic:
> Subgroup prune-stale-modes:
> pass -> SKIP (snb-x220t)
> Test kms_pipe_crc_basic:
> Subgroup read-crc-pipe-b-frame-sequence:
> dmesg-warn -> PASS (snb-x220t)
> Subgroup read-crc-pipe-c-frame-sequence:
> dmesg-warn -> PASS (hsw-gt2)
> Test pm_rpm:
> Subgroup basic-pci-d3-state:
> fail -> DMESG-FAIL (snb-x220t)
This basic-pci-d3-state failure shouldn't be caused by
this specific patch. It was filed in bugzilla a few months
back and hasn't been fixed yet.
https://bugs.freedesktop.org/show_bug.cgi?id=93123
> Subgroup basic-rte:
> dmesg-warn -> PASS (hsw-brixbox)
>
> bdw-nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip:12
> bdw-ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip:21
> bsw-nuc-2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
> byt-nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip:35
> hsw-brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip:22
> hsw-gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip:17
> ivb-t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip:25
> skl-i5k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-i7k-2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> skl-nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip:11
> snb-x220t total:194 pass:159 dwarn:0 dfail:1 fail:0 skip:34
>
> Results at /archive/results/CI_IGT_test/Patchwork_1628/
>
> 8a9a911d489fe160df173580277983dac5952ed0 drm-intel-nightly: 2016y-03m-17d-10h-02m-10s UTC integration manifest
> f432d2fe29fb024ac515e2ad2a7a8bb9700e6c70 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-17 1:06 ` [PATCH] " Dongwon Kim
@ 2016-03-22 9:10 ` Imre Deak
2016-03-22 17:33 ` dw kim
2016-04-11 10:00 ` Imre Deak
1 sibling, 1 reply; 11+ messages in thread
From: Imre Deak @ 2016-03-22 9:10 UTC (permalink / raw
To: Dongwon Kim, intel-gfx
On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> For BXT, description of polarities of PORT_PLL_REF_SEL
> has been reversed for newer Gen9LP steppings according to the
> recent update in Bspec. This bit now should be set for
> "Non-SSC" mode for all Gen9LP starting from B0 stepping.
>
> v2: Only B0 and newer stepping should be affected by this
> change.
What is this stepping information based on? It's not in BSpec, could
you file a change request to get it added there?
--Imre
>
> Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 4b636c4..c84589e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1285,7 +1285,15 @@ static void bxt_ddi_pll_enable(struct
> drm_i915_private *dev_priv,
> enum port port = (enum port)pll->id; /* 1:1 port->PLL
> mapping */
>
> temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> - temp &= ~PORT_PLL_REF_SEL;
> + /*
> + * Definition of each bit polarity has been changed
> + * after A1 stepping
> + */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + temp &= ~PORT_PLL_REF_SEL;
> + else
> + temp |= PORT_PLL_REF_SEL;
> +
> /* Non-SSC reference */
> I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-22 9:10 ` Imre Deak
@ 2016-03-22 17:33 ` dw kim
0 siblings, 0 replies; 11+ messages in thread
From: dw kim @ 2016-03-22 17:33 UTC (permalink / raw
To: Deak, Imre; +Cc: intel-gfx@lists.freedesktop.org
On Tue, Mar 22, 2016 at 02:10:47AM -0700, Deak, Imre wrote:
> On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> > For BXT, description of polarities of PORT_PLL_REF_SEL
> > has been reversed for newer Gen9LP steppings according to the
> > recent update in Bspec. This bit now should be set for
> > "Non-SSC" mode for all Gen9LP starting from B0 stepping.
> >
> > v2: Only B0 and newer stepping should be affected by this
> > change.
>
> What is this stepping information based on? It's not in BSpec, could
> you file a change request to get it added there?
>
> --Imre
That information is actually missing in Bspec and has to be added.
I got this info from the owner of the HSD sighting directly. I will
file a change request in Bspec.
>
> >
> > Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++++++-
> > 1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 4b636c4..c84589e 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -1285,7 +1285,15 @@ static void bxt_ddi_pll_enable(struct
> > drm_i915_private *dev_priv,
> > enum port port = (enum port)pll->id; /* 1:1 port->PLL
> > mapping */
> >
> > temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> > - temp &= ~PORT_PLL_REF_SEL;
> > + /*
> > + * Definition of each bit polarity has been changed
> > + * after A1 stepping
> > + */
> > + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> > + temp &= ~PORT_PLL_REF_SEL;
> > + else
> > + temp |= PORT_PLL_REF_SEL;
> > +
> > /* Non-SSC reference */
> > I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
> >
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
2016-03-17 1:06 ` [PATCH] " Dongwon Kim
2016-03-22 9:10 ` Imre Deak
@ 2016-04-11 10:00 ` Imre Deak
1 sibling, 0 replies; 11+ messages in thread
From: Imre Deak @ 2016-04-11 10:00 UTC (permalink / raw
To: Dongwon Kim, intel-gfx
On ke, 2016-03-16 at 18:06 -0700, Dongwon Kim wrote:
> For BXT, description of polarities of PORT_PLL_REF_SEL
> has been reversed for newer Gen9LP steppings according to the
> recent update in Bspec. This bit now should be set for
> "Non-SSC" mode for all Gen9LP starting from B0 stepping.
>
> v2: Only B0 and newer stepping should be affected by this
> change.
>
> Signed-off-by: Dongwon Kim <dongwon.kim@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94866
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 4b636c4..c84589e 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -1285,7 +1285,15 @@ static void bxt_ddi_pll_enable(struct
> drm_i915_private *dev_priv,
> enum port port = (enum port)pll->id; /* 1:1 port->PLL
> mapping */
>
> temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
> - temp &= ~PORT_PLL_REF_SEL;
> + /*
> + * Definition of each bit polarity has been changed
> + * after A1 stepping
> + */
> + if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> + temp &= ~PORT_PLL_REF_SEL;
> + else
> + temp |= PORT_PLL_REF_SEL;
> +
> /* Non-SSC reference */
> I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2)
2016-03-17 18:05 ` dw kim
@ 2016-04-11 10:10 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2016-04-11 10:10 UTC (permalink / raw
To: dw kim, intel-gfx
On to, 2016-03-17 at 11:05 -0700, dw kim wrote:
> On Thu, Mar 17, 2016 at 01:03:36PM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit
> > (rev2)
> > URL : https://patchwork.freedesktop.org/series/4491/
> > State : failure
> >
> > == Summary ==
> >
> > Series 4491v2 drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL
> > bit
> > http://patchwork.freedesktop.org/api/1.0/series/4491/revisions/2/mb
> > ox/
> >
> > Test drv_module_reload_basic:
> > dmesg-warn -> PASS (hsw-gt2)
> > Test gem_ringfill:
> > Subgroup basic-default-s3:
> > dmesg-warn -> PASS (bsw-nuc-2)
> > Test kms_flip:
> > Subgroup basic-flip-vs-dpms:
> > dmesg-warn -> PASS (bdw-ultra)
> > Subgroup basic-flip-vs-wf_vblank:
> > fail -> PASS (snb-x220t)
> > Subgroup basic-plain-flip:
> > pass -> DMESG-WARN (hsw-gt2)
> > dmesg-warn -> PASS (hsw-brixbox)
> > Test kms_force_connector_basic:
> > Subgroup prune-stale-modes:
> > pass -> SKIP (snb-x220t)
> > Test kms_pipe_crc_basic:
> > Subgroup read-crc-pipe-b-frame-sequence:
> > dmesg-warn -> PASS (snb-x220t)
> > Subgroup read-crc-pipe-c-frame-sequence:
> > dmesg-warn -> PASS (hsw-gt2)
> > Test pm_rpm:
> > Subgroup basic-pci-d3-state:
> > fail -> DMESG-FAIL (snb-x220t)
>
> This basic-pci-d3-state failure shouldn't be caused by
> this specific patch. It was filed in bugzilla a few months
> back and hasn't been fixed yet.
>
> https://bugs.freedesktop.org/show_bug.cgi?id=93123
All the above failures were due to the WM programming w/o powerref
issue which was fixed meanwhile.
Thanks for the patch I pushed it to drm-intel-next-queued.
--Imre
>
> > Subgroup basic-rte:
> > dmesg-warn -> PASS (hsw-brixbox)
> >
> > bdw-
> > nuci7 total:194 pass:182 dwarn:0 dfail:0 fail:0 skip
> > :12
> > bdw-
> > ultra total:194 pass:173 dwarn:0 dfail:0 fail:0 skip
> > :21
> > bsw-nuc-
> > 2 total:194 pass:157 dwarn:0 dfail:0 fail:0 skip:37
> > byt-
> > nuc total:194 pass:155 dwarn:4 dfail:0 fail:0 skip
> > :35
> > hsw-
> > brixbox total:194 pass:172 dwarn:0 dfail:0 fail:0 skip
> > :22
> > hsw-
> > gt2 total:194 pass:176 dwarn:1 dfail:0 fail:0 skip
> > :17
> > ivb-
> > t430s total:194 pass:169 dwarn:0 dfail:0 fail:0 skip
> > :25
> > skl-i5k-
> > 2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> > skl-i7k-
> > 2 total:194 pass:171 dwarn:0 dfail:0 fail:0 skip:23
> > skl-
> > nuci5 total:194 pass:183 dwarn:0 dfail:0 fail:0 skip
> > :11
> > snb-
> > x220t total:194 pass:159 dwarn:0 dfail:1 fail:0 skip
> > :34
> >
> > Results at /archive/results/CI_IGT_test/Patchwork_1628/
> >
> > 8a9a911d489fe160df173580277983dac5952ed0 drm-intel-nightly: 2016y-
> > 03m-17d-10h-02m-10s UTC integration manifest
> > f432d2fe29fb024ac515e2ad2a7a8bb9700e6c70 drm/i915/bxt: Reversed
> > polarity of PORT_PLL_REF_SEL bit
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2016-04-11 10:10 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-03-15 23:37 [PATCH] drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit Dongwon Kim
2016-03-16 9:01 ` Imre Deak
2016-03-16 11:58 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-03-16 16:58 ` dw kim
2016-03-17 1:06 ` [PATCH] " Dongwon Kim
2016-03-22 9:10 ` Imre Deak
2016-03-22 17:33 ` dw kim
2016-04-11 10:00 ` Imre Deak
2016-03-17 13:03 ` ✗ Fi.CI.BAT: failure for drm/i915/bxt: Reversed polarity of PORT_PLL_REF_SEL bit (rev2) Patchwork
2016-03-17 18:05 ` dw kim
2016-04-11 10:10 ` Imre Deak
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