From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751434AbdJ3ESL (ORCPT ); Mon, 30 Oct 2017 00:18:11 -0400 Received: from mail-pg0-f44.google.com ([74.125.83.44]:46243 "EHLO mail-pg0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750750AbdJ3ESK (ORCPT ); Mon, 30 Oct 2017 00:18:10 -0400 X-Google-Smtp-Source: ABhQp+TKIq2HZERaCPs2DpHVNn6NUc7jIEOroeBGZR4f2y1/Ar1LOAFXNIzyG5S2Vwpkj+kdNd8NkQ== Date: Mon, 30 Oct 2017 13:18:06 +0900 From: Stafford Horne To: Marc Zyngier Cc: LKML , Stefan Kristiansson , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Jonas Bonn , "David S. Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap , devicetree@vger.kernel.org, openrisc@lists.librecores.org Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> <86mv4974ht.fsf@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86mv4974ht.fsf@arm.com> User-Agent: Mutt/1.9.1 (2017-09-22) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote: > On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > > From: Stefan Kristiansson > > > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > > described in the Multi-core support section of the OpenRISC 1.2 > > architecture specification: > > > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > > > Each OpenRISC core contains a full interrupt controller which is used in > > the SMP architecture for interrupt balancing. This IPI device, the > > ompic, is the only external device required for enabling SMP on > > OpenRISC. > > > > Pending ops are stored in a memory bit mask which can allow multiple > > pending operations to be set and serviced at a time. This is mostly > > borrowed from the alpha IPI implementation. > > > > Cc: Marc Zyngier > > Acked-by: Rob Herring > > Signed-off-by: Stefan Kristiansson > > [shorne@gmail.com: converted ops to bitmask, wrote commit message] > > Signed-off-by: Stafford Horne > > Reviewed-by: Marc Zyngier Thanks > Side question: what is your merge strategy for this? I can take it > through the irqchip tree as it is standalone, but I'm open to other > suggestions. For me its easier if I just take it through the openrisc tree, as there are dependencies between this series and the irqchip driver. If you are ok with that I can make a note to Linus indicating so in the pull request. My plan is to send this series during the 4.15 merge window. -Stafford From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stafford Horne Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic Date: Mon, 30 Oct 2017 13:18:06 +0900 Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> <86mv4974ht.fsf@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <86mv4974ht.fsf-5wv7dgnIgG8@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Marc Zyngier Cc: LKML , Stefan Kristiansson , Thomas Gleixner , Jason Cooper , Rob Herring , Mark Rutland , Jonas Bonn , "David S. Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, openrisc-cunTk1MwBs9a3B2Vnqf2dGD2FQJk+8+b@public.gmane.org List-Id: devicetree@vger.kernel.org On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote: > On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > > From: Stefan Kristiansson > > > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > > described in the Multi-core support section of the OpenRISC 1.2 > > architecture specification: > > > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > > > Each OpenRISC core contains a full interrupt controller which is used in > > the SMP architecture for interrupt balancing. This IPI device, the > > ompic, is the only external device required for enabling SMP on > > OpenRISC. > > > > Pending ops are stored in a memory bit mask which can allow multiple > > pending operations to be set and serviced at a time. This is mostly > > borrowed from the alpha IPI implementation. > > > > Cc: Marc Zyngier > > Acked-by: Rob Herring > > Signed-off-by: Stefan Kristiansson > > [shorne-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: converted ops to bitmask, wrote commit message] > > Signed-off-by: Stafford Horne > > Reviewed-by: Marc Zyngier Thanks > Side question: what is your merge strategy for this? I can take it > through the irqchip tree as it is standalone, but I'm open to other > suggestions. For me its easier if I just take it through the openrisc tree, as there are dependencies between this series and the irqchip driver. If you are ok with that I can make a note to Linus indicating so in the pull request. My plan is to send this series during the 4.15 merge window. -Stafford -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stafford Horne Date: Mon, 30 Oct 2017 13:18:06 +0900 Subject: [OpenRISC] [PATCH v4 05/13] irqchip: add initial support for ompic In-Reply-To: <86mv4974ht.fsf@arm.com> References: <20171029231123.27281-1-shorne@gmail.com> <20171029231123.27281-6-shorne@gmail.com> <86mv4974ht.fsf@arm.com> Message-ID: <20171030041806.GA29237@lianli.shorne-pla.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: openrisc@lists.librecores.org On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote: > On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne wrote: > > From: Stefan Kristiansson > > > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as > > described in the Multi-core support section of the OpenRISC 1.2 > > architecture specification: > > > > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf > > > > Each OpenRISC core contains a full interrupt controller which is used in > > the SMP architecture for interrupt balancing. This IPI device, the > > ompic, is the only external device required for enabling SMP on > > OpenRISC. > > > > Pending ops are stored in a memory bit mask which can allow multiple > > pending operations to be set and serviced at a time. This is mostly > > borrowed from the alpha IPI implementation. > > > > Cc: Marc Zyngier > > Acked-by: Rob Herring > > Signed-off-by: Stefan Kristiansson > > [shorne at gmail.com: converted ops to bitmask, wrote commit message] > > Signed-off-by: Stafford Horne > > Reviewed-by: Marc Zyngier Thanks > Side question: what is your merge strategy for this? I can take it > through the irqchip tree as it is standalone, but I'm open to other > suggestions. For me its easier if I just take it through the openrisc tree, as there are dependencies between this series and the irqchip driver. If you are ok with that I can make a note to Linus indicating so in the pull request. My plan is to send this series during the 4.15 merge window. -Stafford