From: James Hogan <james.hogan@mips.com>
To: Paul Cercueil <paul@crapouillou.net>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Maarten ter Huurne <maarten@treewalker.org>,
Paul Burton <paul.burton@mips.com>,
<linux-kernel@vger.kernel.org>, <linux-mips@linux-mips.org>
Subject: Re: [PATCH v6 11/15] MIPS: ingenic: Initial JZ4770 support
Date: Wed, 10 Jan 2018 22:42:34 +0000 [thread overview]
Message-ID: <20180110224233.GV27409@jhogan-linux.mipstec.com> (raw)
In-Reply-To: <20180105182513.16248-12-paul@crapouillou.net>
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On Fri, Jan 05, 2018 at 07:25:09PM +0100, Paul Cercueil wrote:
> Provide just enough bits (clocks, clocksource, uart) to allow a kernel
> to boot on the JZ4770 SoC to a initramfs userspace.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> ---
> arch/mips/boot/dts/ingenic/jz4770.dtsi | 212 +++++++++++++++++++++++++++++++++
> arch/mips/jz4740/Kconfig | 6 +
> arch/mips/jz4740/time.c | 2 +-
> 3 files changed, 219 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/ingenic/jz4770.dtsi
We should probably have a MAINTAINERS entry including this file. Same
goes for the GC0 files added in the last patch.
Cheers
James
>
> v2: No change
> v3: No change
> v4: No change
> v5: Use SPDX license identifier
> v6: No change
>
> diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> new file mode 100644
> index 000000000000..7c2804f3f5f1
> --- /dev/null
> +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> @@ -0,0 +1,212 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/clock/jz4770-cgu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ingenic,jz4770";
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + intc: interrupt-controller@10001000 {
> + compatible = "ingenic,jz4770-intc";
> + reg = <0x10001000 0x40>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + ext: ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + osc32k: osc32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + cgu: jz4770-cgu@10000000 {
> + compatible = "ingenic,jz4770-cgu";
> + reg = <0x10000000 0x100>;
> +
> + clocks = <&ext>, <&osc32k>;
> + clock-names = "ext", "osc32k";
> +
> + #clock-cells = <1>;
> + };
> +
> + pinctrl: pin-controller@10010000 {
> + compatible = "ingenic,jz4770-pinctrl";
> + reg = <0x10010000 0x600>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpa: gpio@0 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <0>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <17>;
> + };
> +
> + gpb: gpio@1 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <1>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <16>;
> + };
> +
> + gpc: gpio@2 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <2>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <15>;
> + };
> +
> + gpd: gpio@3 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <3>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <14>;
> + };
> +
> + gpe: gpio@4 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <4>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 128 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <13>;
> + };
> +
> + gpf: gpio@5 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <5>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 160 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <12>;
> + };
> + };
> +
> + uart0: serial@10030000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10030000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <5>;
> +
> + status = "disabled";
> + };
> +
> + uart1: serial@10031000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10031000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <4>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@10032000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10032000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <3>;
> +
> + status = "disabled";
> + };
> +
> + uart3: serial@10033000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10033000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <2>;
> +
> + status = "disabled";
> + };
> +
> + uhc: uhc@13430000 {
> + compatible = "generic-ohci";
> + reg = <0x13430000 0x1000>;
> +
> + clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
> + assigned-clocks = <&cgu JZ4770_CLK_UHC>;
> + assigned-clock-rates = <48000000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <20>;
> +
> + status = "disabled";
> + };
> +};
> diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
> index 643af2012e14..29a9361a2b77 100644
> --- a/arch/mips/jz4740/Kconfig
> +++ b/arch/mips/jz4740/Kconfig
> @@ -18,6 +18,12 @@ config MACH_JZ4740
> bool
> select SYS_HAS_CPU_MIPS32_R1
>
> +config MACH_JZ4770
> + bool
> + select MIPS_CPU_SCACHE
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_SUPPORTS_HIGHMEM
> +
> config MACH_JZ4780
> bool
> select MIPS_CPU_SCACHE
> diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
> index bb1ad5119da4..2ca9160f642a 100644
> --- a/arch/mips/jz4740/time.c
> +++ b/arch/mips/jz4740/time.c
> @@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = {
> #ifdef CONFIG_MACH_JZ4740
> .irq = JZ4740_IRQ_TCU0,
> #endif
> -#ifdef CONFIG_MACH_JZ4780
> +#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
> .irq = JZ4780_IRQ_TCU2,
> #endif
> };
> --
> 2.11.0
>
>
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WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@mips.com>
To: Paul Cercueil <paul@crapouillou.net>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Maarten ter Huurne <maarten@treewalker.org>,
Paul Burton <paul.burton@mips.com>,
linux-kernel@vger.kernel.org, linux-mips@linux-mips.org
Subject: Re: [PATCH v6 11/15] MIPS: ingenic: Initial JZ4770 support
Date: Wed, 10 Jan 2018 22:42:34 +0000 [thread overview]
Message-ID: <20180110224233.GV27409@jhogan-linux.mipstec.com> (raw)
Message-ID: <20180110224234.krnf4EL1_UJgE7zCus9pE2EUjt7AFA5cUcp-410EJVA@z> (raw)
In-Reply-To: <20180105182513.16248-12-paul@crapouillou.net>
[-- Attachment #1: Type: text/plain, Size: 6865 bytes --]
On Fri, Jan 05, 2018 at 07:25:09PM +0100, Paul Cercueil wrote:
> Provide just enough bits (clocks, clocksource, uart) to allow a kernel
> to boot on the JZ4770 SoC to a initramfs userspace.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Reviewed-by: PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
> ---
> arch/mips/boot/dts/ingenic/jz4770.dtsi | 212 +++++++++++++++++++++++++++++++++
> arch/mips/jz4740/Kconfig | 6 +
> arch/mips/jz4740/time.c | 2 +-
> 3 files changed, 219 insertions(+), 1 deletion(-)
> create mode 100644 arch/mips/boot/dts/ingenic/jz4770.dtsi
We should probably have a MAINTAINERS entry including this file. Same
goes for the GC0 files added in the last patch.
Cheers
James
>
> v2: No change
> v3: No change
> v4: No change
> v5: Use SPDX license identifier
> v6: No change
>
> diff --git a/arch/mips/boot/dts/ingenic/jz4770.dtsi b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> new file mode 100644
> index 000000000000..7c2804f3f5f1
> --- /dev/null
> +++ b/arch/mips/boot/dts/ingenic/jz4770.dtsi
> @@ -0,0 +1,212 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <dt-bindings/clock/jz4770-cgu.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ingenic,jz4770";
> +
> + cpuintc: interrupt-controller {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + intc: interrupt-controller@10001000 {
> + compatible = "ingenic,jz4770-intc";
> + reg = <0x10001000 0x40>;
> +
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + ext: ext {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + osc32k: osc32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + cgu: jz4770-cgu@10000000 {
> + compatible = "ingenic,jz4770-cgu";
> + reg = <0x10000000 0x100>;
> +
> + clocks = <&ext>, <&osc32k>;
> + clock-names = "ext", "osc32k";
> +
> + #clock-cells = <1>;
> + };
> +
> + pinctrl: pin-controller@10010000 {
> + compatible = "ingenic,jz4770-pinctrl";
> + reg = <0x10010000 0x600>;
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + gpa: gpio@0 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <0>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 0 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <17>;
> + };
> +
> + gpb: gpio@1 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <1>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 32 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <16>;
> + };
> +
> + gpc: gpio@2 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <2>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 64 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <15>;
> + };
> +
> + gpd: gpio@3 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <3>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 96 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <14>;
> + };
> +
> + gpe: gpio@4 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <4>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 128 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <13>;
> + };
> +
> + gpf: gpio@5 {
> + compatible = "ingenic,jz4770-gpio";
> + reg = <5>;
> +
> + gpio-controller;
> + gpio-ranges = <&pinctrl 0 160 32>;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <12>;
> + };
> + };
> +
> + uart0: serial@10030000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10030000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <5>;
> +
> + status = "disabled";
> + };
> +
> + uart1: serial@10031000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10031000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <4>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@10032000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10032000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <3>;
> +
> + status = "disabled";
> + };
> +
> + uart3: serial@10033000 {
> + compatible = "ingenic,jz4770-uart";
> + reg = <0x10033000 0x100>;
> +
> + clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
> + clock-names = "baud", "module";
> +
> + interrupt-parent = <&intc>;
> + interrupts = <2>;
> +
> + status = "disabled";
> + };
> +
> + uhc: uhc@13430000 {
> + compatible = "generic-ohci";
> + reg = <0x13430000 0x1000>;
> +
> + clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
> + assigned-clocks = <&cgu JZ4770_CLK_UHC>;
> + assigned-clock-rates = <48000000>;
> +
> + interrupt-parent = <&intc>;
> + interrupts = <20>;
> +
> + status = "disabled";
> + };
> +};
> diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
> index 643af2012e14..29a9361a2b77 100644
> --- a/arch/mips/jz4740/Kconfig
> +++ b/arch/mips/jz4740/Kconfig
> @@ -18,6 +18,12 @@ config MACH_JZ4740
> bool
> select SYS_HAS_CPU_MIPS32_R1
>
> +config MACH_JZ4770
> + bool
> + select MIPS_CPU_SCACHE
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_SUPPORTS_HIGHMEM
> +
> config MACH_JZ4780
> bool
> select MIPS_CPU_SCACHE
> diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
> index bb1ad5119da4..2ca9160f642a 100644
> --- a/arch/mips/jz4740/time.c
> +++ b/arch/mips/jz4740/time.c
> @@ -113,7 +113,7 @@ static struct clock_event_device jz4740_clockevent = {
> #ifdef CONFIG_MACH_JZ4740
> .irq = JZ4740_IRQ_TCU0,
> #endif
> -#ifdef CONFIG_MACH_JZ4780
> +#if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
> .irq = JZ4780_IRQ_TCU2,
> #endif
> };
> --
> 2.11.0
>
>
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next prev parent reply other threads:[~2018-01-10 22:43 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-02 15:08 [PATCH v5 01/15] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 03/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 04/15] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 05/15] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-05 16:34 ` Rob Herring
2018-01-05 16:34 ` Rob Herring
2018-01-02 15:08 ` [PATCH v5 06/15] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-02 17:05 ` Mathieu Malaterre
2018-01-02 15:08 ` [PATCH v5 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-02 15:58 ` PrasannaKumar Muralidharan
2018-01-02 15:58 ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-02 15:59 ` PrasannaKumar Muralidharan
2018-01-02 15:59 ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 10/15] MIPS: ingenic: Add machine info for supported boards Paul Cercueil
2018-01-02 16:02 ` PrasannaKumar Muralidharan
2018-01-02 16:32 ` Paul Cercueil
2018-01-02 16:32 ` Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-02 16:09 ` PrasannaKumar Muralidharan
2018-01-02 16:09 ` PrasannaKumar Muralidharan
2018-01-02 15:08 ` [PATCH v5 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2018-01-02 15:08 ` Paul Cercueil
2018-01-02 16:45 ` PrasannaKumar Muralidharan
2018-01-05 18:03 ` Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-02 15:08 ` [PATCH v5 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-01-02 17:04 ` Mathieu Malaterre
2018-01-05 18:24 ` [PATCH v6 00/15] JZ4770 SoC support Paul Cercueil
2018-01-05 18:24 ` [PATCH v6 01/15] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 00/14] JZ4770 and GCW0 patchset Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 01/14] clk: ingenic: Use const pointer to clk_ops in struct Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 02/14] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 03/14] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 04/14] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 05/14] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 06/14] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 07/14] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 08/14] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-16 15:47 ` [PATCH v7 09/14] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-16 15:48 ` [PATCH v7 10/14] MIPS: ingenic: Detect machtype from SoC compatible string Paul Cercueil
2018-01-16 22:06 ` James Hogan
2018-01-16 15:48 ` [PATCH v7 11/14] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-17 21:28 ` James Hogan
2018-01-17 21:28 ` James Hogan
2018-01-18 17:14 ` Paul Cercueil
2018-01-18 20:30 ` James Hogan
2018-01-18 20:30 ` James Hogan
2018-01-16 15:48 ` [PATCH v7 12/14] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-16 15:48 ` [PATCH v7 13/14] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-16 15:48 ` [PATCH v7 14/14] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-02-01 15:31 ` [PATCH v7 00/14] JZ4770 and GCW0 patchset James Hogan
2018-01-05 18:25 ` [PATCH v6 02/15] clk: ingenic: Fix recalc_rate for clocks with fixed divider Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 03/15] clk: ingenic: support PLLs with no bypass bit Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 04/15] clk: ingenic: Add code to enable/disable PLLs Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 05/15] dt-bindings: clock: Add jz4770-cgu.h header Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 06/15] clk: Add Ingenic jz4770 CGU driver Paul Cercueil
2018-01-10 21:37 ` James Hogan
2018-01-10 21:37 ` James Hogan
2018-01-05 18:25 ` [PATCH v6 07/15] MIPS: Setup boot_command_line before plat_mem_setup Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 08/15] MIPS: ingenic: Use common cmdline handling code Paul Cercueil
2018-01-10 22:16 ` James Hogan
2018-01-10 22:16 ` James Hogan
2018-01-05 18:25 ` [PATCH v6 09/15] MIPS: platform: add machtype IDs for more Ingenic SoCs Paul Cercueil
2018-01-10 22:19 ` James Hogan
2018-01-10 22:19 ` James Hogan
2018-01-05 18:25 ` [PATCH v6 10/15] MIPS: ingenic: Detect machtype from SoC compatible string Paul Cercueil
2018-01-10 22:27 ` James Hogan
2018-01-10 22:27 ` James Hogan
2018-01-16 14:06 ` Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 11/15] MIPS: ingenic: Initial JZ4770 support Paul Cercueil
2018-01-10 22:42 ` James Hogan [this message]
2018-01-10 22:42 ` James Hogan
2018-01-05 18:25 ` [PATCH v6 12/15] MIPS: JZ4770: Work around config2 misreporting associativity Paul Cercueil
2018-01-10 22:52 ` James Hogan
2018-01-10 22:52 ` James Hogan
2018-01-05 18:25 ` [PATCH v6 13/15] MIPS: JZ4770: Workaround for corrupted DMA transfers Paul Cercueil
2018-01-10 23:20 ` James Hogan
2018-01-10 23:20 ` James Hogan
2018-01-16 14:10 ` Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 14/15] devicetree/bindings: Add GCW vendor prefix Paul Cercueil
2018-01-05 18:25 ` [PATCH v6 15/15] MIPS: ingenic: Initial GCW Zero support Paul Cercueil
2018-01-07 16:18 ` Philippe Ombredanne
2018-01-10 22:59 ` Paul Cercueil
2018-01-23 10:31 ` Philippe Ombredanne
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