* [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
@ 2018-07-06 14:23 Chris Wilson
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Chris Wilson @ 2018-07-06 14:23 UTC (permalink / raw
To: intel-gfx
Replace the magic bit with the proper symbolic name for instructing
MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT
address (still virtual!) on gen4+.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem_coherency.c | 4 ++--
drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
4 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
index 1193dd36913a..ab662dabcff7 100644
--- a/drivers/gpu/drm/i915/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
@@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
*cmd++ = val;
} else if (gen >= 4) {
*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? 1 << 22 : 0);
+ (gen < 6 ? MI_USE_GGTT : 0);
*cmd++ = 0;
*cmd++ = offset;
*cmd++ = val;
} else {
- *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+ *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*cmd++ = offset;
*cmd++ = val;
}
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
index cb9eef1635e1..294c58aba2c1 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
@@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
*cs++ = v;
} else if (INTEL_GEN(i915) >= 4) {
- *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
*cs++ = i915_ggtt_offset(vma) + offset;
*cs++ = v;
} else {
- *cs++ = MI_STORE_DWORD_IMM | 1 << 22;
+ *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*cs++ = i915_ggtt_offset(vma) + offset;
*cs++ = v;
*cs++ = MI_NOOP;
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
index 0d8e719802fa..65100d3e31cf 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
@@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
*cmd++ = value;
} else if (gen >= 4) {
*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
- (gen < 6 ? 1 << 22 : 0);
+ (gen < 6 ? MI_USE_GGTT : 0);
*cmd++ = 0;
*cmd++ = offset;
*cmd++ = value;
} else {
- *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
+ *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*cmd++ = offset;
*cmd++ = value;
}
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 5cb808dc5b50..0fc6da81f86e 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h,
*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
*batch++ = lower_32_bits(vma->node.start);
} else if (INTEL_GEN(i915) >= 4) {
- *batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
+ *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = rq->fence.seqno;
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
@ 2018-07-06 14:23 ` Chris Wilson
2018-07-06 14:47 ` Ville Syrjälä
2018-07-06 14:47 ` [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Ville Syrjälä
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Chris Wilson @ 2018-07-06 14:23 UTC (permalink / raw
To: intel-gfx
We always want to use a virtual address (i.e. use the GTT) for
MI_STORE_DWORD_IMM, but forgot the ever so important flag in
live_hangcheck for gen3.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
index 0fc6da81f86e..c838f7d08cb9 100644
--- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
+++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
@@ -184,7 +184,7 @@ static int emit_recurse_batch(struct hang *h,
*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
*batch++ = lower_32_bits(vma->node.start);
} else {
- *batch++ = MI_STORE_DWORD_IMM;
+ *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = rq->fence.seqno;
*batch++ = MI_ARB_CHECK;
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
@ 2018-07-06 14:47 ` Ville Syrjälä
2018-07-06 14:53 ` Chris Wilson
2018-07-06 16:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2018-07-07 13:17 ` ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Ville Syrjälä @ 2018-07-06 14:47 UTC (permalink / raw
To: Chris Wilson; +Cc: intel-gfx
On Fri, Jul 06, 2018 at 03:23:22PM +0100, Chris Wilson wrote:
> Replace the magic bit with the proper symbolic name for instructing
> MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT
> address (still virtual!) on gen4+.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/selftests/huge_pages.c | 4 ++--
> drivers/gpu/drm/i915/selftests/i915_gem_coherency.c | 4 ++--
> drivers/gpu/drm/i915/selftests/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
> 4 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 1193dd36913a..ab662dabcff7 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
> *cmd++ = val;
> } else if (gen >= 4) {
> *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
> - (gen < 6 ? 1 << 22 : 0);
> + (gen < 6 ? MI_USE_GGTT : 0);
> *cmd++ = 0;
> *cmd++ = offset;
> *cmd++ = val;
> } else {
> - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
> + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *cmd++ = offset;
> *cmd++ = val;
> }
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> index cb9eef1635e1..294c58aba2c1 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
> *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
> *cs++ = v;
Missed the gen8+ case here?
> } else if (INTEL_GEN(i915) >= 4) {
> - *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
So here we use ggtt on all gens. In the other tests we use ppgtt on
gen6+. Ah, this one uses the kernel context apparently. I guess that's
the reason?
> *cs++ = 0;
> *cs++ = i915_ggtt_offset(vma) + offset;
> *cs++ = v;
> } else {
> - *cs++ = MI_STORE_DWORD_IMM | 1 << 22;
> + *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *cs++ = i915_ggtt_offset(vma) + offset;
> *cs++ = v;
> *cs++ = MI_NOOP;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 0d8e719802fa..65100d3e31cf 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
> *cmd++ = value;
> } else if (gen >= 4) {
> *cmd++ = MI_STORE_DWORD_IMM_GEN4 |
> - (gen < 6 ? 1 << 22 : 0);
> + (gen < 6 ? MI_USE_GGTT : 0);
> *cmd++ = 0;
> *cmd++ = offset;
> *cmd++ = value;
> } else {
> - *cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
> + *cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *cmd++ = offset;
> *cmd++ = value;
> }
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 5cb808dc5b50..0fc6da81f86e 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h,
> *batch++ = MI_BATCH_BUFFER_START | 1 << 8;
> *batch++ = lower_32_bits(vma->node.start);
> } else if (INTEL_GEN(i915) >= 4) {
> - *batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> + *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = rq->fence.seqno;
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
@ 2018-07-06 14:47 ` Ville Syrjälä
0 siblings, 0 replies; 7+ messages in thread
From: Ville Syrjälä @ 2018-07-06 14:47 UTC (permalink / raw
To: Chris Wilson; +Cc: intel-gfx
On Fri, Jul 06, 2018 at 03:23:23PM +0100, Chris Wilson wrote:
> We always want to use a virtual address (i.e. use the GTT) for
> MI_STORE_DWORD_IMM, but forgot the ever so important flag in
> live_hangcheck for gen3.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 0fc6da81f86e..c838f7d08cb9 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -184,7 +184,7 @@ static int emit_recurse_batch(struct hang *h,
> *batch++ = MI_BATCH_BUFFER_START | 2 << 6;
> *batch++ = lower_32_bits(vma->node.start);
> } else {
> - *batch++ = MI_STORE_DWORD_IMM;
> + *batch++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = rq->fence.seqno;
> *batch++ = MI_ARB_CHECK;
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
2018-07-06 14:47 ` [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Ville Syrjälä
@ 2018-07-06 14:53 ` Chris Wilson
0 siblings, 0 replies; 7+ messages in thread
From: Chris Wilson @ 2018-07-06 14:53 UTC (permalink / raw
To: Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2018-07-06 15:47:25)
> On Fri, Jul 06, 2018 at 03:23:22PM +0100, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> > index cb9eef1635e1..294c58aba2c1 100644
> > --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> > +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> > @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
> > *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
> > *cs++ = v;
>
> Missed the gen8+ case here?
>
> > } else if (INTEL_GEN(i915) >= 4) {
> > - *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> > + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>
> So here we use ggtt on all gens. In the other tests we use ppgtt on
> gen6+. Ah, this one uses the kernel context apparently. I guess that's
> the reason?
If memory serves, yes, this was deliberately trying to use the ppGTT in
this case. I guess I need to check this against the full-ppgtt patches
for gen7 (although shard-hsw didn't flag anything iirc), but this should
probably have a (gen < 6 ? MI_USE_GGTT : 0) here.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
2018-07-06 14:47 ` [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Ville Syrjälä
@ 2018-07-06 16:03 ` Patchwork
2018-07-07 13:17 ` ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-07-06 16:03 UTC (permalink / raw
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
URL : https://patchwork.freedesktop.org/series/46078/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4446 -> Patchwork_9570 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46078/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9570 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
fi-skl-guc: PASS -> FAIL (fdo#103191)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-kbl-7567u: PASS -> FAIL (fdo#103191)
==== Warnings ====
igt@gem_exec_suspend@basic-s4-devices:
{fi-kbl-8809g}: DMESG-WARN (fdo#107139) -> INCOMPLETE (fdo#107139)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
== Participating hosts (47 -> 42) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4446 -> Patchwork_9570
CI_DRM_4446: 95944426a9ffda186843c78f2f925494e1bc53c5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4543: 366eed37c7c71217e1cb1f3be5e26358a41f0001 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9570: 4ece3280cdc43e239759fe44f8e94ab5b1dba570 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4ece3280cdc4 drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck
58f72e75d92e drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9570/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
` (2 preceding siblings ...)
2018-07-06 16:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
@ 2018-07-07 13:17 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-07-07 13:17 UTC (permalink / raw
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
URL : https://patchwork.freedesktop.org/series/46078/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4446_full -> Patchwork_9570_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9570_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9570_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9570_full:
=== IGT changes ===
==== Possible regressions ====
igt@kms_universal_plane@cursor-fb-leak-pipe-b:
shard-apl: PASS -> FAIL
==== Warnings ====
igt@gem_exec_schedule@deep-bsd1:
shard-kbl: SKIP -> PASS +1
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9570_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_rotation_crc@primary-rotation-270:
shard-apl: PASS -> FAIL (fdo#103925)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
==== Possible fixes ====
igt@gem_workarounds@suspend-resume-context:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
shard-glk: FAIL (fdo#106509) -> PASS
igt@kms_universal_plane@cursor-fb-leak-pipe-c:
shard-apl: FAIL -> PASS
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4446 -> Patchwork_9570
CI_DRM_4446: 95944426a9ffda186843c78f2f925494e1bc53c5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4543: 366eed37c7c71217e1cb1f3be5e26358a41f0001 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9570: 4ece3280cdc43e239759fe44f8e94ab5b1dba570 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9570/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-07-07 13:17 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
2018-07-06 14:47 ` Ville Syrjälä
2018-07-06 14:47 ` [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Ville Syrjälä
2018-07-06 14:53 ` Chris Wilson
2018-07-06 16:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2018-07-07 13:17 ` ✗ Fi.CI.IGT: failure " Patchwork
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